common: Drop linux/bitops.h from common header

[platform/kernel/u-boot.git] / drivers / clk / altera / clk-arria10.c

diff --git a/drivers/clk/altera/clk-arria10.c b/drivers/clk/altera/clk-arria10.c
index 78102c7..ede0be2 100644 (file)
--- a/drivers/clk/altera/clk-arria10.c
+++ b/drivers/clk/altera/clk-arria10.c
@@ -4,11 +4,15 @@
  */
 
 #include <common.h>
+#include <malloc.h>
 #include <asm/io.h>
 #include <clk-uclass.h>
 #include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
 #include <dm/lists.h>
 #include <dm/util.h>
+#include <linux/bitops.h>
 
 #include <asm/arch/clock_manager.h>
 
@@ -254,7 +258,8 @@ static int socfpga_a10_clk_bind(struct udevice *dev)
                    fdt_node_check_compatible(fdt, offset, "fixed-clock"))
                        continue;
 
-               if (pre_reloc_only && !dm_fdt_pre_reloc(fdt, offset))
+               if (pre_reloc_only &&
+                   !ofnode_pre_reloc(offset_to_ofnode(offset)))
                        continue;
 
                ret = device_bind_driver_to_node(dev, "clk-a10", name,
@@ -270,6 +275,8 @@ static int socfpga_a10_clk_bind(struct udevice *dev)
 static int socfpga_a10_clk_probe(struct udevice *dev)
 {
        struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);
+       struct socfpga_a10_clk_platdata *pplat;
+       struct udevice *pdev;
        const void *fdt = gd->fdt_blob;
        int offset = dev_of_offset(dev);
 
@@ -277,6 +284,21 @@ static int socfpga_a10_clk_probe(struct udevice *dev)
 
        socfpga_a10_handoff_workaround(dev);
 
+       if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) {
+               plat->regs = devfdt_get_addr(dev);
+       } else {
+               pdev = dev_get_parent(dev);
+               if (!pdev)
+                       return -ENODEV;
+
+               pplat = dev_get_platdata(pdev);
+               if (!pplat)
+                       return -EINVAL;
+
+               plat->ctl_reg = dev_read_u32_default(dev, "reg", 0x0);
+               plat->regs = pplat->regs;
+       }
+
        if (!fdt_node_check_compatible(fdt, offset,
                                       "altr,socfpga-a10-pll-clock")) {
                /* Main PLL has 3 upstream clock */
@@ -300,29 +322,8 @@ static int socfpga_a10_clk_probe(struct udevice *dev)
 static int socfpga_a10_ofdata_to_platdata(struct udevice *dev)
 {
        struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);
-       struct socfpga_a10_clk_platdata *pplat;
-       struct udevice *pdev;
-       const void *fdt = gd->fdt_blob;
        unsigned int divreg[3], gatereg[2];
-       int ret, offset = dev_of_offset(dev);
-       u32 regs;
-
-       regs = dev_read_u32_default(dev, "reg", 0x0);
-
-       if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) {
-               plat->regs = devfdt_get_addr(dev);
-       } else {
-               pdev = dev_get_parent(dev);
-               if (!pdev)
-                       return -ENODEV;
-
-               pplat = dev_get_platdata(pdev);
-               if (!pplat)
-                       return -EINVAL;
-
-               plat->ctl_reg = regs;
-               plat->regs = pplat->regs;
-       }
+       int ret;
 
        plat->type = SOCFPGA_A10_CLK_UNKNOWN_CLK;
 
@@ -352,7 +353,6 @@ static const struct udevice_id socfpga_a10_clk_match[] = {
 U_BOOT_DRIVER(socfpga_a10_clk) = {
        .name           = "clk-a10",
        .id             = UCLASS_CLK,
-       .flags          = DM_FLAG_PRE_RELOC,
        .of_match       = socfpga_a10_clk_match,
        .ops            = &socfpga_a10_clk_ops,
        .bind           = socfpga_a10_clk_bind,