#include <linux/libata.h>
#define DRV_NAME "pata_hpt37x"
-#define DRV_VERSION "0.6.5"
+#define DRV_VERSION "0.6.6"
struct hpt_clock {
u8 xfer_speed;
/**
* hpt37x_pre_reset - reset the hpt37x bus
* @ap: ATA port to reset
+ * @deadline: deadline jiffies for the operation
*
* Perform the initial reset handling for the 370/372 and 374 func 0
*/
-static int hpt37x_pre_reset(struct ata_port *ap)
+static int hpt37x_pre_reset(struct ata_port *ap, unsigned long deadline)
{
u8 scr2, ata66;
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
udelay(100);
- return ata_std_prereset(ap);
+ return ata_std_prereset(ap, deadline);
}
/**
ata_bmdma_drive_eh(ap, hpt37x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}
-static int hpt374_pre_reset(struct ata_port *ap)
+static int hpt374_pre_reset(struct ata_port *ap, unsigned long deadline)
{
static const struct pci_bits hpt37x_enable_bits[] = {
{ 0x50, 1, 0x04, 0x04 },
pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
udelay(100);
- return ata_std_prereset(ap);
+ return ata_std_prereset(ap, deadline);
}
/**
static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
/* HPT370 - UDMA100 */
- static struct ata_port_info info_hpt370 = {
+ static const struct ata_port_info info_hpt370 = {
.sht = &hpt37x_sht,
- .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
+ .flags = ATA_FLAG_SLAVE_POSS,
.pio_mask = 0x1f,
.mwdma_mask = 0x07,
- .udma_mask = 0x3f,
+ .udma_mask = ATA_UDMA5,
.port_ops = &hpt370_port_ops
};
/* HPT370A - UDMA100 */
- static struct ata_port_info info_hpt370a = {
+ static const struct ata_port_info info_hpt370a = {
.sht = &hpt37x_sht,
- .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
+ .flags = ATA_FLAG_SLAVE_POSS,
.pio_mask = 0x1f,
.mwdma_mask = 0x07,
- .udma_mask = 0x3f,
+ .udma_mask = ATA_UDMA5,
.port_ops = &hpt370a_port_ops
};
/* HPT370 - UDMA100 */
- static struct ata_port_info info_hpt370_33 = {
+ static const struct ata_port_info info_hpt370_33 = {
.sht = &hpt37x_sht,
- .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
+ .flags = ATA_FLAG_SLAVE_POSS,
.pio_mask = 0x1f,
.mwdma_mask = 0x07,
.udma_mask = 0x0f,
.port_ops = &hpt370_port_ops
};
/* HPT370A - UDMA100 */
- static struct ata_port_info info_hpt370a_33 = {
+ static const struct ata_port_info info_hpt370a_33 = {
.sht = &hpt37x_sht,
- .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
+ .flags = ATA_FLAG_SLAVE_POSS,
.pio_mask = 0x1f,
.mwdma_mask = 0x07,
.udma_mask = 0x0f,
.port_ops = &hpt370a_port_ops
};
/* HPT371, 372 and friends - UDMA133 */
- static struct ata_port_info info_hpt372 = {
+ static const struct ata_port_info info_hpt372 = {
.sht = &hpt37x_sht,
- .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
+ .flags = ATA_FLAG_SLAVE_POSS,
.pio_mask = 0x1f,
.mwdma_mask = 0x07,
- .udma_mask = 0x7f,
+ .udma_mask = ATA_UDMA6,
.port_ops = &hpt372_port_ops
};
- /* HPT371, 372 and friends - UDMA100 at 50MHz clock */
- static struct ata_port_info info_hpt372_50 = {
+ /* HPT374 - UDMA100 */
+ static const struct ata_port_info info_hpt374 = {
.sht = &hpt37x_sht,
- .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
+ .flags = ATA_FLAG_SLAVE_POSS,
.pio_mask = 0x1f,
.mwdma_mask = 0x07,
- .udma_mask = 0x3f,
- .port_ops = &hpt372_port_ops
- };
- /* HPT374 - UDMA133 */
- static struct ata_port_info info_hpt374 = {
- .sht = &hpt37x_sht,
- .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
- .pio_mask = 0x1f,
- .mwdma_mask = 0x07,
- .udma_mask = 0x7f,
+ .udma_mask = ATA_UDMA5,
.port_ops = &hpt374_port_ops
};
static const int MHz[4] = { 33, 40, 50, 66 };
-
- struct ata_port_info *port_info[2];
- struct ata_port_info *port;
+ const struct ata_port_info *port;
+ void *private_data = NULL;
+ struct ata_port_info port_info;
+ const struct ata_port_info *ppi[] = { &port_info, NULL };
u8 irqmask;
u32 class_rev;
u8 mcr1;
u32 freq;
int prefer_dpll = 1;
-
+
unsigned long iobase = pci_resource_start(dev, 4);
const struct hpt_chip *chip_table;
*/
pci_write_config_byte(dev, 0x5b, 0x23);
-
+
/*
* HighPoint does this for HPT372A.
* NOTE: This register is only writeable via I/O space.
* Turn the frequency check into a band and then find a timing
* table to match it.
*/
-
+
clock_slot = hpt37x_clock_slot(freq, chip_table->base);
if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
/*
* use a 50MHz DPLL by choice
*/
unsigned int f_low, f_high;
- int adjust;
-
- clock_slot = 2;
+ int dpll, adjust;
+
+ /* Compute DPLL */
+ dpll = 2;
if (port->udma_mask & 0xE0)
- clock_slot = 3;
-
- f_low = (MHz[clock_slot] * chip_table->base) / 192;
+ dpll = 3;
+
+ f_low = (MHz[clock_slot] * 48) / MHz[dpll];
f_high = f_low + 2;
+ if (clock_slot > 1)
+ f_high += 2;
/* Select the DPLL clock. */
pci_write_config_byte(dev, 0x5b, 0x21);
+ pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
for(adjust = 0; adjust < 8; adjust++) {
if (hpt37x_calibrate_dpll(dev))
printk(KERN_WARNING "hpt37x: DPLL did not stabilize.\n");
return -ENODEV;
}
- if (clock_slot == 3)
- port->private_data = (void *)hpt37x_timings_66;
+ if (dpll == 3)
+ private_data = (void *)hpt37x_timings_66;
else
- port->private_data = (void *)hpt37x_timings_50;
+ private_data = (void *)hpt37x_timings_50;
- printk(KERN_INFO "hpt37x: Bus clock %dMHz, using DPLL.\n", MHz[clock_slot]);
+ printk(KERN_INFO "hpt37x: Bus clock %dMHz, using DPLL.\n", MHz[dpll]);
} else {
- port->private_data = (void *)chip_table->clocks[clock_slot];
+ private_data = (void *)chip_table->clocks[clock_slot];
/*
* Perform a final fixup. Note that we will have used the
* DPLL on the HPT372 which means we don't have to worry
printk(KERN_INFO "hpt37x: %s: Bus clock %dMHz.\n", chip_table->name, MHz[clock_slot]);
}
- port_info[0] = port_info[1] = port;
/* Now kick off ATA set up */
- return ata_pci_init_one(dev, port_info, 2);
+ port_info = *port;
+ port_info.private_data = private_data;
+
+ return ata_pci_init_one(dev, ppi);
}
static const struct pci_device_id hpt37x[] = {