; Infineon XC16X CPU description. -*- Scheme -*-
;
-; Copyright 2006, 2007 Free Software Foundation, Inc.
+; Copyright 2006, 2007, 2009 Free Software Foundation, Inc.
;
; Contributed by KPIT Cummins Infosystems Ltd.; developed under contract
; from Infineon Systems, GMBH , Germany.
; Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
; 02110-1301, USA.
+(define-rtl-version 0 8)
+
(include "simplify.inc")
; define-arch appears first
(define-keyword
(name gr-names)
- (print-name h-gr)
- (prefix "")
+ (enum-prefix H-GR-)
(values (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
(r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15))
(indices extern-keyword gr-names)
)
+;; HACK: Various semantics refer to h-cr.
+;; This is here to keep things working.
+(define-hardware
+ (name h-cr)
+ (comment "cr registers")
+ (attrs PROFILE CACHE-ADDR)
+ (type register HI (16))
+ (indices extern-keyword gr-names)
+)
+
(define-keyword
(name ext-names)
- (print-name h-ext)
- (prefix "")
+ (enum-prefix H-EXT-)
(values (0x1 0) (0x2 1) (0x3 2) (0x4 3)
("1" 0) ("2" 1) ("3" 2) ("4" 3))
(define-keyword
(name psw-names)
- (print-name h-psw)
- (prefix "")
+ (enum-prefix H-PSW-)
(values ("IEN" 136) ("r0.11" 240) ("r1.11" 241) ("r2.11" 242) ("r3.11" 243) ("r4.11" 244)
("r5.11" 245) ("r6.11" 246) ("r7.11" 247) ("r8.11" 248)
("r9.11" 249) ("r10.11" 250) ("r11.11" 251) ("r12.11" 252)
(define-keyword
(name grb-names)
- (print-name h-grb)
- (prefix "")
+ (enum-prefix H-GRB-)
(values (rl0 0) (rh0 1) (rl1 2) (rh1 3) (rl2 4) (rh2 5) (rl3 6) (rh3 7)
(rl4 8) (rh4 9) (rl5 10) (rh5 11) (rl6 12) (rh6 13) (rl7 14) (rh7 15))
)
(define-keyword
(name conditioncode-names)
- (print-name h-cc)
- (prefix "")
+ (enum-prefix H-CC-)
(values (cc_UC 0) (cc_NET 1) (cc_Z 2) (cc_EQ 2) (cc_NZ 3) (cc_NE 3) (cc_V 4) (cc_NV 5) (cc_N 6) (cc_NN 7) (cc_ULT 8) (cc_UGE 9)
(cc_C 8) (cc_NC 9) (cc_SGT 10) (cc_SLE 11) (cc_SLT 12) (cc_SGE 13) (cc_UGT 14)
(cc_ULE 15))
(define-keyword
(name extconditioncode-names)
- (print-name h-ecc)
- (prefix "")
+ (enum-prefix H-ECC-)
(values(cc_UC 0) (cc_NET 2) (cc_Z 4) (cc_EQ 4) (cc_NZ 6) (cc_NE 6) (cc_V 8) (cc_NV 10) (cc_N 12) (cc_NN 14) (cc_ULT 16) (cc_UGE 18) (cc_C 16) (cc_NC 18) (cc_SGT 20)
(cc_SLE 22) (cc_SLT 24) (cc_SGE 26) (cc_UGT 28) (cc_ULE 30) (cc_nusr0 1)
(cc_nusr1 3) (cc_usr0 5) (cc_usr1 7))
(define-keyword
(name grb8-names)
- (print-name h-grb8)
- (prefix "")
+ (enum-prefix H-GRB8-)
(values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3)
(psw 136) (cp 8) (mdl 7) (mdh 6)
(mdc 135) (sp 9) (csp 4) (vecseg 137)
(define-keyword
(name r8-names)
- (print-name h-r8)
- (prefix "")
+ (enum-prefix H-R8-)
(values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3)
(psw 136) (cp 8) (mdl 7) (mdh 6)
(mdc 135) (sp 9) (csp 4) (vecseg 137)
(define-keyword
(name regmem8-names)
- (print-name h-regmem8)
- (prefix "")
+ (enum-prefix H-REGMEM8-)
(values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3)
(psw 136) (cp 8) (mdl 7) (mdh 6)
(mdc 135) (sp 9) (csp 4) (vecseg 137)
(define-keyword
(name regdiv8-names)
- (print-name h-regdiv8)
- (prefix "")
+ (enum-prefix H-REGDIV8-)
(values (r0 0) (r1 17) (r2 34) (r3 51) (r4 68) (r5 85) (r6 102) (r7 119)
(r8 136) (r9 153) (r10 170) (r11 187) (r12 204) (r13 221) (r14 238) (r15 255))
)
(define-keyword
(name reg0-name)
- (print-name h-reg0)
- (prefix "")
+ (enum-prefix H-REG0-)
(values (0x1 1) (0x2 2) (0x3 3) (0x4 4) (0x5 5) (0x6 6) (0x7 7) (0x8 8) (0x9 9) (0xa 10) (0xb 11)
(0xc 12) (0xd 13) (0xe 14) (0xf 15)
("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) ("11" 11)
(define-keyword
(name reg0-name1)
- (print-name h-reg01)
- (prefix "")
+ (enum-prefix H-REG01-)
(values (0x1 1) (0x2 2) (0x3 3) (0x4 4) (0x5 5) (0x6 6) (0x7 7)
("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7))
)
(define-keyword
(name regbmem8-names)
- (print-name h-regbmem8)
- (prefix "")
+ (enum-prefix H-REGBMEM8-)
(values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3)
(psw 136) (cp 8) (mdl 7) (mdh 6)
(mdc 135) (sp 9) (csp 4) (vecseg 137)
(define-keyword
(name memgr8-names)
- (print-name h-memgr8)
- (prefix "")
+ (enum-prefix H-MEMGR8-)
(values (dpp0 65024) (dpp1 65026) (dpp2 65028) (dpp3 65030)
(psw 65296) (cp 65040) (mdl 65038) (mdh 65036)
(mdc 65294) (sp 65042) (csp 65032) (vecseg 65298)
(comment "segment")
)
+;; Define an operand that takes a set of handlers.
+;; dowh: define-operand-with-handlers
+(define-pmacro (dowh x-name x-comment x-attrs x-type x-index x-handlers)
+ (define-operand (name x-name) (comment x-comment)
+ (.splice attrs (.unsplice x-attrs))
+ (type x-type) (index x-index)
+ (.splice handlers (.unsplice x-handlers)))
+)
+
(dnop sr "source register" () h-gr f-r2)
(dnop dr "destination register" () h-gr f-r1)
(dnop dri "destination register" () h-gr f-r4)
(dnop uimm7 "7 bit trap number" (HASH-PREFIX) h-uint f-uimm7)
(dnop uimm8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm8)
(dnop uimm16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm16)
-(dnop upof16 "16 bit unsigned immediate" (POF-PREFIX) h-addr f-memory)
+(dowh upof16 "16 bit unsigned immediate" (POF-PREFIX) h-addr f-memory ((print "with_pof_prefix")))
(dnop reg8 "8 bit word register number" () h-r8 f-reg8)
(dnop regmem8 "8 bit word register number" () h-regmem8 f-regmem8)
(dnop regbmem8 "8 bit byte register number" () h-regbmem8 f-regmem8)
(dnop memory "16 bit memory" () h-addr f-memory)
(dnop memgr8 "16 bit memory" () h-memgr8 f-memgr8)
(dnop cbit "carry bit" (SEM-ONLY) h-cbit f-nil)
-(dnop qbit "bit addr" (DOT-PREFIX) h-uint f-qbit)
-(dnop qlobit "bit addr" (DOT-PREFIX) h-uint f-qlobit)
-(dnop qhibit "bit addr" (DOT-PREFIX) h-uint f-qhibit)
+(dowh qbit "bit addr" (DOT-PREFIX) h-uint f-qbit ((print "with_dot_prefix")))
+(dowh qlobit "bit addr" (DOT-PREFIX) h-uint f-qlobit ((print "with_dot_prefix")))
+(dowh qhibit "bit addr" (DOT-PREFIX) h-uint f-qhibit ((print "with_dot_prefix")))
(dnop mask8 "8 bit mask" (HASH-PREFIX) h-uint f-mask8)
(dnop masklo8 "8 bit mask" (HASH-PREFIX) h-uint f-datahi8)
(dnop pagenum "10 bit page number" (HASH-PREFIX) h-uint f-pagenum)
(dnop data8 "8 bit data" (HASH-PREFIX) h-uint f-data8)
(dnop datahi8 "8 bit data" (HASH-PREFIX) h-uint f-datahi8)
(dnop sgtdisbit "segmentation enable bit" (SEM-ONLY) h-sgtdis f-nil)
-(dnop upag16 "16 bit unsigned immediate" (PAG-PREFIX) h-uint f-uimm16)
+(dowh upag16 "16 bit unsigned immediate" (PAG-PREFIX) h-uint f-uimm16 ((print "with_pag_prefix")))
(dnop useg8 "8 bit segment " (SEG-PREFIX) h-uint f-seg8)
(dnop useg16 "16 bit address offset" (SEG-PREFIX) h-uint f-offset16)
(dnop usof16 "16 bit address offset" (SOF-PREFIX) h-uint f-offset16)
((PIPE OS) (IDOC ALU))
"mul $src1,$src2"
(+ OP1_0 OP2_11 src1 src2)
- (reg SI h-md 0)
+ (nop) ;; FIXME: (reg SI h-md 0)
()
)
; MULU Rwn,Rwm
((PIPE OS) (IDOC ALU))
"mulu $src1,$src2"
(+ OP1_1 OP2_11 src1 src2)
- (reg SI h-md 0)
+ (nop) ;; FIXME: (reg SI h-md 0)
()
)
; DIV Rwn
"divl $srdiv"
(+ OP1_6 OP2_11 srdiv )
(sequence ()
- (set HI (reg HI h-cr 6) (div SI (reg SI h-md 0) srdiv))
- (set HI (reg HI h-cr 7) (mod SI (reg SI h-md 0) srdiv))
+ (set HI (reg HI h-cr 6) 0) ;; FIXME: (div SI (reg SI h-md 0) srdiv))
+ (set HI (reg HI h-cr 7) 0) ;; FIXME: (mod SI (reg SI h-md 0) srdiv))
)
()
)
"divlu $srdiv"
(+ OP1_7 OP2_11 srdiv )
(sequence ()
- (set HI (reg HI h-cr 6) (udiv SI (reg SI h-md 0) srdiv))
- (set HI (reg HI h-cr 7) (umod SI (reg SI h-md 0) srdiv))
+ (set HI (reg HI h-cr 6) 0) ;; FIXME: (udiv SI (reg SI h-md 0) srdiv))
+ (set HI (reg HI h-cr 7) 0) ;; FIXME: (umod SI (reg SI h-md 0) srdiv))
)
()
)
((PIPE OS) (IDOC MOVE))
(.str insn " [-$"op2 "],$"op1)
(+ opc1 opc2 op1 op2)
- (sequence HI ()
+ (sequence ()
(set op1 (sub op2 (const HI 2)))
(set HI (mem HI op2) op1)
)
((PIPE OS) (IDOC MOVE))
(.str insn " $"op1 ",[$"op2"+$hash$"uimm16"]")
(+ opc1 opc2 op1 op2 uimm16)
- (sequence mode ((mode tmp1))
+ (sequence ((mode tmp1))
(set mode tmp1 (add HI op2 uimm16))
(set mode op1 (mem HI tmp1))
)
((PIPE OS) (IDOC MOVE))
(.str insn " [$"op2"+$hash$"uimm16 "],$"op1)
(+ opc1 opc2 op1 op2 uimm16)
- (sequence mode ((mode tmp1))
+ (sequence ((mode tmp1))
(set mode tmp1 (add HI op1 uimm16))
(set mode (mem HI tmp1) op1)
)
"movbs $sr,$drb"
(+ OP1_13 OP2_0 drb sr)
(sequence ()
- (if QI (and QI drb (const 128))
- (set HI sr (or HI (const HI 65280) drb)))
+ (if (and QI drb (const 128))
+ (set HI sr (or HI (const HI 65280) drb)))
(set HI sr (and HI (const HI 255) drb))
)
()
(.str insn " $"op2 ",$"op1)
(+ opc1 opc2 op1 op2)
(sequence ()
- (if QI (and QI op1 (const 128))
- (set HI op2 (or HI (const HI 65280) op1)))
+ (if (and QI op1 (const 128))
+ (set HI op2 (or HI (const HI 65280) op1)))
(set HI op2 (and HI (const HI 255) op1))
)
()
(sequence ((HI tmp1) (HI tmp2))
(set tmp1 (mem HI caddr))
(set tmp2 (sub HI pc (mem HI caddr)))
- (if (gt tmp2 (const 0)) (lt tmp2 (const 32)) (eq tmp2 (const 32))
+ (if (gt tmp2 (const 0)) ;; FIXME: (lt tmp2 (const 32)) (eq tmp2 (const 32))
(set bitone (const 1)))
- (if (lt tmp2 (const 0)) (eq tmp2 (const 0)) (gt tmp2 (const 32))
+ (if (lt tmp2 (const 0)) ;; FIXME: (eq tmp2 (const 0)) (gt tmp2 (const 32))
(set bitone (const 0)))
- (if (eq extcond (const 1) (ne extcond cc_Z))
+ (if (eq extcond (const 1)) ;; FIXME: (ne extcond cc_Z))
(set bit01 (const 0))
(set HI pc (mem HI caddr)))
- (if (ne extcond (const 1) (eq extcond cc_Z))
+ (if (ne extcond (const 1)) ;; FIXME: (eq extcond cc_Z))
(set bit01 (const 1))
(set HI pc (add HI pc (const 2))))
)
(sequence ((HI tmp1) (HI tmp2))
(set tmp1 (mem HI caddr))
(set tmp2 (sub HI pc (mem HI caddr)))
- (if (gt tmp2 (const 0)) (lt tmp2 (const 32)) (eq tmp2 (const 32))
+ (if (gt tmp2 (const 0)) ;; FIXME: (lt tmp2 (const 32)) (eq tmp2 (const 32))
(set bitone (const 1)))
- (if (lt tmp2 (const 0)) (eq tmp2 (const 0)) (gt tmp2 (const 32))
+ (if (lt tmp2 (const 0)) ;; FIXME: (eq tmp2 (const 0)) (gt tmp2 (const 32))
(set bitone (const 0)))
(set HI pc (add HI pc (const 2)))
)
(sequence ()
(if (eq cond (const 1))
(sequence ()
- (if QI (lt QI rel (const 0))
- (sequence ()
- (neg QI rel)
- (add QI rel (const 1))
- (mul QI rel (const 2))
- (set HI pc (sub HI pc rel))
- ))
+ (if (lt QI rel (const 0))
+ (sequence ()
+ ;; FIXME: (neg QI rel)
+ ;; FIXME: (add QI rel (const 1))
+ ;; FIXME: (mul QI rel (const 2))
+ (set HI pc (sub HI pc rel))
+ ))
(set HI pc (add HI pc (mul QI rel (const 2))))
)
)
"jmps $hash$segm$useg8,$hash$sof$usof16"
(+ OP1_15 OP2_10 seg usof16)
(sequence ()
- (if QI (eq BI sgtdisbit (const BI 0))
- (set QI (reg h-cr 10) useg8))
- (nop)
+ (if (eq BI sgtdisbit (const BI 0))
+ (set QI (reg h-cr 10) useg8))
+ ;; FIXME: previous indentation suggested this nop was the `else'
+ ;; clause of the previous `if'.
+ (nop)
(set HI pc usof16)
)
()
"jmps $seg,$caddr"
(+ OP1_15 OP2_10 seg caddr)
(sequence ()
- (if QI (eq BI sgtdisbit (const BI 0))
- (set QI (reg h-cr 10) seg))
- (nop)
+ (if (eq BI sgtdisbit (const BI 0))
+ (set QI (reg h-cr 10) seg))
+ ;; FIXME: previous indentation suggested this nop was the `else'
+ ;; clause of the previous `if'.
+ (nop)
(set HI pc caddr)
)
()
(sequence ((HI tmp1) (HI tmp2))
(set HI tmp1 genreg)
(set HI tmp2 (const 1))
- (sll HI tmp2 qlobit)
+ ;;(sll HI tmp2 qlobit) - FIXME: missing (set ...)
(set HI tmp2 (and tmp1 tmp2))
- (if (eq tmp2 (const 1))
+ (if (eq tmp2 (const 1)) ;; FIXME: (ne tmp2 0)?
(sequence ()
- (if QI (lt QI relhi (const 0))
- (set HI pc (add HI pc (mul QI relhi (const 2)))))
+ (if (lt QI relhi (const 0))
+ (set HI pc (add HI pc (mul QI relhi (const 2)))))
))
- (set HI pc (add HI pc (const 4)))
+ (set HI pc (add HI pc (const 4))) ;; FIXME: Is this right?
)
()
)
(sequence ((HI tmp1) (HI tmp2))
(set HI tmp1 genreg)
(set HI tmp2 (const 1))
- (sll HI tmp2 qlobit)
+ ;;(sll HI tmp2 qlobit) - FIXME: missing (set ...)
(set HI tmp2 (and tmp1 tmp2))
- (if (eq tmp2 (const 1))
+ (if (eq tmp2 (const 1)) ;; FIXME: (ne tmp2 0)?
(sequence ()
- (if QI (lt QI relhi (const 0))
- (set tmp2 (const 1))
- (set tmp1 genreg)
- (sll tmp2 qlobit)
- (inv tmp2)
- (set HI tmp1(and tmp1 tmp2))
- (set HI genreg tmp1)
- (set HI pc (add HI pc (mul QI relhi (const 2)))))
+ ;; FIXME: The `else' clause has several statements.
+ (if (lt QI relhi (const 0))
+ (set tmp2 (const 1))
+ (set tmp1 genreg)
+ ;; FIXME: (sll tmp2 qlobit)
+ ;; FIXME: (inv tmp2)
+ (set HI tmp1 (and tmp1 tmp2))
+ (set HI genreg tmp1)
+ (set HI pc (add HI pc (mul QI relhi (const 2)))))
))
- (set HI pc (add HI pc (const 4)))
+ (set HI pc (add HI pc (const 4))) ;; FIXME: Is this right?
)
()
)
(sequence ((HI tmp1) (HI tmp2))
(set HI tmp1 genreg)
(set HI tmp2 (const 1))
- (sll HI tmp2 qlobit)
+ ;;(sll HI tmp2 qlobit) - FIXME: missing (set ...)
(set HI tmp2 (and tmp1 tmp2))
- (if (eq tmp2 (const 0))
+ (if (eq tmp2 (const 0)) ;; FIXME: (ne tmp2 0)?
(sequence ()
- (if QI (lt QI relhi (const 0))
- (set HI pc (add HI pc (mul QI relhi (const 2)))))
+ (if (lt QI relhi (const 0))
+ (set HI pc (add HI pc (mul QI relhi (const 2)))))
))
- (set HI pc (add HI pc (const 4)))
+ (set HI pc (add HI pc (const 4))) ;; FIXME: Is this right?
)
()
)
(sequence ((HI tmp1) (HI tmp2))
(set HI tmp1 genreg)
(set HI tmp2 (const 1))
- (sll HI tmp2 qlobit)
+ ;;(sll HI tmp2 qlobit) - FIXME: missing (set ...)
(set HI tmp2 (and tmp1 tmp2))
(if (eq tmp2 (const 0))
(sequence ()
- (if QI (lt QI relhi (const 0))
- (set tmp2 (const 1))
- (set tmp1 reg8)
- (sll tmp2 qbit)
- (set BI tmp1(or tmp1 tmp2))
- (set HI reg8 tmp1)
- (set HI pc (add HI pc (mul QI relhi (const 2)))))
+ ;; FIXME: The `else' clause has several statements.
+ (if (lt QI relhi (const 0))
+ (set tmp2 (const 1))
+ (set tmp1 reg8)
+ ;; FIXME: (sll tmp2 qbit)
+ (set BI tmp1(or tmp1 tmp2))
+ (set HI reg8 tmp1)
+ (set HI pc (add HI pc (mul QI relhi (const 2)))))
))
- (set HI pc (add HI pc (const 4)))
+ (set HI pc (add HI pc (const 4))) ;; FIXME: Is this right?
)
()
)
(set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
(set HI (mem HI (reg h-cr 9)) pc)
(sequence ()
- (if QI (lt QI rel (const 0))
- (sequence ()
- (neg QI rel)
- (add QI rel (const 1))
- (mul QI rel (const 2))
- (set HI pc (sub HI pc rel))
- ))
+ (if (lt QI rel (const 0))
+ (sequence ()
+ ;; FIXME: (neg QI rel)
+ ;; FIXME: (add QI rel (const 1))
+ ;; FIXME: (mul QI rel (const 2))
+ (set HI pc (sub HI pc rel))
+ ))
(set HI pc (add HI pc (mul QI rel (const 2))))
)
)
(set HI (mem HI (reg h-cr 9)) (reg h-cr 10))
(set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
(set HI (mem HI (reg h-cr 9)) pc)
- (if QI (eq BI sgtdisbit (const BI 0))
- (set QI (reg h-cr 10) useg8))
- (nop)
+ (if (eq BI sgtdisbit (const BI 0))
+ (set QI (reg h-cr 10) useg8))
+ ;; FIXME: previous indentation suggested this nop was the `else'
+ ;; clause of the previous `if'.
+ (nop)
(set HI pc usof16)
)
()
(set HI (mem HI (reg h-cr 9)) (reg h-cr 10))
(set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
(set HI (mem HI (reg h-cr 9)) pc)
- (if QI (eq BI sgtdisbit (const BI 0))
- (set QI (reg h-cr 10) seg))
- (nop)
+ (if (eq BI sgtdisbit (const BI 0))
+ (set QI (reg h-cr 10) seg))
+ ;; FIXME: previous indentation suggested this nop was the `else'
+ ;; clause of the previous `if'.
+ (nop)
(set HI pc caddr)
)
()
(sequence ()
(set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
(set HI (mem HI (reg h-cr 9)) (reg h-cr 4))
- (if QI (eq BI sgtdisbit (const BI 0))
- (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
- (set HI (mem HI (reg h-cr 9)) (reg h-cr 10) )
- )
- (nop)
+ (if (eq BI sgtdisbit (const BI 0))
+ (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
+ (set HI (mem HI (reg h-cr 9)) (reg h-cr 10) )
+ )
+ (nop)
(set HI (reg h-cr 10) (reg h-cr 11))
(set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
(set HI (mem HI (reg h-cr 9)) pc)
(sequence ()
(set HI pc (mem HI (reg h-cr 9)))
(set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
- (if QI (eq BI sgtdisbit (const BI 0))
- (set HI (reg h-cr 10) (mem HI (reg h-cr 9)))
- )
- (nop)
+ (if (eq BI sgtdisbit (const BI 0))
+ (set HI (reg h-cr 10) (mem HI (reg h-cr 9)))
+ )
+ (nop)
(set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
)
()
(sequence ()
(set HI pc (mem HI (reg h-cr 9)))
(set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
- (if QI (eq BI sgtdisbit (const BI 0))
- (sequence ()
- (set HI (reg h-cr 10) (mem HI (reg h-cr 9)))
- (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
- )
- )
- (nop)
+ (if (eq BI sgtdisbit (const BI 0))
+ (sequence ()
+ (set HI (reg h-cr 10) (mem HI (reg h-cr 9)))
+ (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
+ )
+ )
+ (nop)
(set HI (reg h-cr 4) (mem HI (reg h-cr 9)))
(set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
)
(sequence ((HI tmp1) (HI tmp2))
(set HI tmp1 reg8)
(set HI tmp2 uimm16)
- (sub HI (reg HI h-cr 9) (const 2))
+ ;; FIXME: (sub HI (reg HI h-cr 9) (const 2))
(set HI (reg HI h-cr 9) tmp1)
(set HI reg8 tmp2)
)
(sequence ((HI tmp1) (HI tmp2))
(set HI tmp1 regmem8)
(set HI tmp2 memgr8)
- (sub HI (reg HI h-cr 9) (const 2))
+ ;; FIXME: (sub HI (reg HI h-cr 9) (const 2))
(set HI (reg HI h-cr 9) tmp1)
(set HI regmem8 tmp2)
)
(sequence ((HI tmp1) (HI tmp2))
(set HI tmp1 reg8)
(set HI tmp2 memory)
- (sub HI (reg HI h-cr 9) (const 2))
+ ;; FIXME: (sub HI (reg HI h-cr 9) (const 2))
(set HI (reg HI h-cr 9) tmp1)
(set HI reg8 tmp2)
)
(+ OP1_13 OP2_1 (f-op-lbit2 0) uimm2 (f-op-bit4 0))
(sequence ((HI count))
(set HI count uimm2)
- (cond HI
+ (cond
((ne HI count (const 0))
(sequence ()
(set HI pc (add HI pc (const 2)))
(+ OP1_13 OP2_1 (f-op-lbit2 2) uimm2 (f-op-bit4 0))
(sequence ((HI count))
(set HI count uimm2)
- (cond HI
+ (cond
((ne HI count (const 0))
(sequence ()
(set HI pc (add HI pc (const 2)))
(+ OP1_13 OP2_12 (f-op-lbit2 1) uimm2 sr)
(sequence ((HI count))
(set HI count uimm2)
- (cond HI
+ (cond
((ne HI count (const 0))
(sequence ()
(set HI pc (add HI pc (const 2)))
(+ OP1_13 OP2_7 (f-op-lbit2 1) uimm2 (f-op-bit4 0) pagenum (f-qlobit 0) (f-qlobit2 0))
(sequence ((HI count))
(set HI count uimm2)
- (cond HI
+ (cond
((ne HI count (const 0))
(sequence ()
(set HI pc (add HI pc (const 2)))
(+ OP1_13 OP2_7 (f-op-lbit2 1) uimm2 (f-op-bit4 0) upag16 )
(sequence ((HI count))
(set HI count uimm2)
- (cond HI
+ (cond
((ne HI count (const 0))
(sequence ()
(set HI pc (add HI pc (const 2)))
(+ OP1_13 OP2_12 (f-op-lbit2 3) uimm2 sr)
(sequence ((HI count))
(set HI count uimm2)
- (cond HI
+ (cond
((ne HI count (const 0))
(sequence ()
(set HI pc (add HI pc (const 2)))
(+ OP1_13 OP2_7 (f-op-lbit2 3) uimm2 (f-op-bit4 0) pagenum (f-qlobit 0) (f-qlobit2 0))
(sequence ((HI count))
(set HI count uimm2)
- (cond HI
+ (cond
((ne HI count (const 0))
(sequence ()
(set HI pc (add HI pc (const 2)))
(+ OP1_13 OP2_12 (f-op-lbit2 0) uimm2 sr)
(sequence ((HI count))
(set HI count uimm2)
- (cond HI
+ (cond
((ne HI count (const 0))
(sequence ()
(set HI pc (add HI pc (const 2)))
(+ OP1_13 OP2_7 (f-op-lbit2 0) uimm2 (f-op-bit4 0) seghi8 (f-op-bit8 0))
(sequence ((HI count))
(set HI count uimm2)
- (cond HI
+ (cond
((ne HI count (const 0))
(sequence ()
(set HI pc (add HI pc (const 2)))
(+ OP1_13 OP2_12 (f-op-lbit2 2) uimm2 sr)
(sequence ((HI count))
(set HI count uimm2)
- (cond HI
+ (cond
((ne HI count (const 0))
(sequence ()
(set HI pc (add HI pc (const 2)))
(+ OP1_13 OP2_7 (f-op-lbit2 2) uimm2 (f-op-bit4 0) seghi8 (f-op-bit8 0))
(sequence ((HI count))
(set HI count uimm2)
- (cond HI
+ (cond
((ne HI count (const 0))
(sequence ()
(set HI pc (add HI pc (const 2)))
(set HI count (const 0))
(set HI tmp1 sr)
(set HI tmp2 (and tmp1 (const 32768)))
- (cond HI
- ((ne HI tmp2 (const 1)) (ne HI sr (const 0))
- (sll HI tmp1 (const 1))
+ (cond
+ ((ne HI tmp2 (const 1)) ;;(ne HI sr (const 0)) - FIXME: and? or?
+ ;;(sll HI tmp1 (const 1)) - FIXME: missing (set ...)
(set HI tmp2 (and tmp1 (const 32768)))
(set HI count (add HI count (const 1)))
)
(sequence ((HI tmp1) (HI tmp2))
(set tmp2 (const 1))
(set tmp1 reg8)
- (sll tmp2 qbit)
- (inv tmp2)
+ ;; FIXME: (sll tmp2 qbit)
+ ;; FIXME: (inv tmp2)
(set BI tmp1(and tmp1 tmp2))
(set HI reg8 tmp1))
()
(sequence ((HI tmp1) (HI tmp2))
(set tmp2 (const 1))
(set tmp1 reg8)
- (sll tmp2 qbit)
- (inv tmp2)
+ ;; FIXME: (sll tmp2 qbit)
+ ;; FIXME: (inv tmp2)
(set BI tmp1(and tmp1 tmp2))
(set HI reg8 tmp1))
()
(sequence ((HI tmp1) (HI tmp2))
(set tmp2 (const 1))
(set tmp1 reg8)
- (sll tmp2 qbit)
+ ;; FIXME: (sll tmp2 qbit)
(set BI tmp1(or tmp1 tmp2))
(set HI reg8 tmp1))
()
(sequence ((HI tmp1) (HI tmp2))
(set tmp2 (const 1))
(set tmp1 reg8)
- (sll tmp2 qbit)
+ ;; FIXME: (sll tmp2 qbit)
(set BI tmp1(or tmp1 tmp2))
(set HI reg8 tmp1))
()
(set HI tmp2 reg8)
(set tmp3 (const 1))
(set tmp4 (const 1))
- (sll tmp3 qlobit)
- (sll tmp4 qhibit)
- (and tmp1 tmp3)
- (and tmp2 tmp4)
+ ;; FIXME: (sll tmp3 qlobit)
+ ;; FIXME: (sll tmp4 qhibit)
+ ;; FIXME: (and tmp1 tmp3)
+ ;; FIXME: (and tmp2 tmp4)
(set BI tmp1 tmp2)
(set HI reghi8 tmp1)
(set HI reg8 tmp2))
(set HI tmp2 reg8)
(set tmp3 (const 1))
(set tmp4 (const 1))
- (sll tmp3 qlobit)
- (sll tmp4 qhibit)
- (and tmp1 tmp3)
- (and tmp2 tmp4)
- (inv HI tmp2)
+ ;; FIXME: (sll tmp3 qlobit)
+ ;; FIXME: (sll tmp4 qhibit)
+ ;; FIXME: (and tmp1 tmp3)
+ ;; FIXME: (and tmp2 tmp4)
+ ;; FIXME: (inv HI tmp2)
(set BI tmp1 tmp2)
(set HI reghi8 tmp1)
(set HI reg8 tmp2))
(set HI tmp2 reg8)
(set tmp3 (const 1))
(set tmp4 (const 1))
- (sll tmp3 qlobit)
- (sll tmp4 qhibit)
- (and tmp1 tmp3)
- (and tmp2 tmp4)
+ ;; FIXME: (sll tmp3 qlobit)
+ ;; FIXME: (sll tmp4 qhibit)
+ ;; FIXME: (and tmp1 tmp3)
+ ;; FIXME: (and tmp2 tmp4)
(set BI tmp1(and tmp1 tmp2))
(set HI reghi8 tmp1)
(set HI reg8 tmp2))
(set HI tmp2 reg8)
(set tmp3 (const 1))
(set tmp4 (const 1))
- (sll tmp3 qlobit)
- (sll tmp4 qhibit)
- (and tmp1 tmp3)
- (and tmp2 tmp4)
+ ;; FIXME: (sll tmp3 qlobit)
+ ;; FIXME: (sll tmp4 qhibit)
+ ;; FIXME: (and tmp1 tmp3)
+ ;; FIXME: (and tmp2 tmp4)
(set BI tmp1(or tmp1 tmp2))
(set HI reghi8 tmp1)
(set HI reg8 tmp2))
(set HI tmp2 reg8)
(set tmp3 (const 1))
(set tmp4 (const 1))
- (sll tmp3 qlobit)
- (sll tmp4 qhibit)
- (and tmp1 tmp3)
- (and tmp2 tmp4)
+ ;; FIXME: (sll tmp3 qlobit)
+ ;; FIXME: (sll tmp4 qhibit)
+ ;; FIXME: (and tmp1 tmp3)
+ ;; FIXME: (and tmp2 tmp4)
(set BI tmp1(xor tmp1 tmp2))
(set HI reghi8 tmp1)
(set HI reg8 tmp2))
(set HI tmp2 reg8)
(set tmp3 (const 1))
(set tmp4 (const 1))
- (sll tmp3 qlobit)
- (sll tmp4 qhibit)
- (and tmp1 tmp3)
- (and tmp2 tmp4)
+ ;; FIXME: (sll tmp3 qlobit)
+ ;; FIXME: (sll tmp4 qhibit)
+ ;; FIXME: (and tmp1 tmp3)
+ ;; FIXME: (and tmp2 tmp4)
(set BI tmp1(xor tmp1 tmp2))
(set HI reghi8 tmp1)
(set HI reg8 tmp2))
(set HI tmp1 reg8)
(set QI tmp2 mask8)
(set QI tmp3 datahi8)
- (inv QI tmp2)
+ ;; FIXME: (inv QI tmp2)
(set HI tmp1 (and tmp1 tmp2))
(set HI tmp1 (or tmp1 tmp3))
(set HI reg8 tmp1)
(set HI tmp1 reg8)
(set QI tmp2 masklo8)
(set HI tmp3 data8)
- (sll tmp2 (const 8))
- (inv HI tmp2)
- (sll tmp3 (const 8))
+ ;; FIXME: (sll tmp2 (const 8))
+ ;; FIXME: (inv HI tmp2)
+ ;; FIXME: (sll tmp3 (const 8))
(set HI tmp1 (and tmp1 tmp2))
(set HI tmp1 (or tmp1 tmp3))
(set HI reg8 tmp1)
projects / external / binutils.git / blobdiff