Merge with /home/stefan/git/u-boot/acadia

[platform/kernel/u-boot.git] / cpu / ppc4xx / start.S

diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index a50d66e..d918b3e 100644 (file)
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -1428,7 +1428,7 @@ ppcSync:
 relocate_code:
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SPE)
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
        /*
         * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
         * to speed up the boot process. Now this cache needs to be disabled.
@@ -1983,43 +1983,43 @@ pll_wait:
 /*----------------------------------------------------------------------------+
 | dcbz_area.
 +----------------------------------------------------------------------------*/
-        function_prolog(dcbz_area)
-        rlwinm. r5,r4,0,27,31
-        rlwinm  r5,r4,27,5,31
-        beq     ..d_ra2
-        addi    r5,r5,0x0001
+       function_prolog(dcbz_area)
+       rlwinm. r5,r4,0,27,31
+       rlwinm  r5,r4,27,5,31
+       beq     ..d_ra2
+       addi    r5,r5,0x0001
 ..d_ra2:mtctr   r5
 ..d_ag2:dcbz    r0,r3
-        addi    r3,r3,32
-        bdnz    ..d_ag2
-        sync
-        blr
-        function_epilog(dcbz_area)
+       addi    r3,r3,32
+       bdnz    ..d_ag2
+       sync
+       blr
+       function_epilog(dcbz_area)
 
 /*----------------------------------------------------------------------------+
 | dflush.  Assume 32K at vector address is cachable.
 +----------------------------------------------------------------------------*/
-        function_prolog(dflush)
-        mfmsr   r9
-        rlwinm  r8,r9,0,15,13
-        rlwinm  r8,r8,0,17,15
-        mtmsr   r8
-        addi    r3,r0,0x0000
-        mtspr   dvlim,r3
-        mfspr   r3,ivpr
-        addi    r4,r0,1024
-        mtctr   r4
+       function_prolog(dflush)
+       mfmsr   r9
+       rlwinm  r8,r9,0,15,13
+       rlwinm  r8,r8,0,17,15
+       mtmsr   r8
+       addi    r3,r0,0x0000
+       mtspr   dvlim,r3
+       mfspr   r3,ivpr
+       addi    r4,r0,1024
+       mtctr   r4
 ..dflush_loop:
-        lwz     r6,0x0(r3)
-        addi    r3,r3,32
-        bdnz    ..dflush_loop
-        addi    r3,r3,-32
-        mtctr   r4
+       lwz     r6,0x0(r3)
+       addi    r3,r3,32
+       bdnz    ..dflush_loop
+       addi    r3,r3,-32
+       mtctr   r4
 ..ag:   dcbf    r0,r3
-        addi    r3,r3,-32
-        bdnz    ..ag
-        sync
-        mtmsr   r9
-        blr
-        function_epilog(dflush)
+       addi    r3,r3,-32
+       bdnz    ..ag
+       sync
+       mtmsr   r9
+       blr
+       function_epilog(dflush)
 #endif /* CONFIG_440 */