ppc: Refactor cache routines, so there is only one common set.

[platform/kernel/u-boot.git] / cpu / ppc4xx / start.S

diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index a730604..c29c87b 100644 (file)
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -1306,39 +1306,6 @@ in32r:
        lwbrx   r3,r0,r3
        blr
 
-/*------------------------------------------------------------------------------- */
-/* Function:    ppcDcbf */
-/* Description:         Data Cache block flush */
-/* Input:       r3 = effective address */
-/* Output:      none. */
-/*------------------------------------------------------------------------------- */
-       .globl  ppcDcbf
-ppcDcbf:
-       dcbf    r0,r3
-       blr
-
-/*------------------------------------------------------------------------------- */
-/* Function:    ppcDcbi */
-/* Description:         Data Cache block Invalidate */
-/* Input:       r3 = effective address */
-/* Output:      none. */
-/*------------------------------------------------------------------------------- */
-       .globl  ppcDcbi
-ppcDcbi:
-       dcbi    r0,r3
-       blr
-
-/*------------------------------------------------------------------------------- */
-/* Function:    ppcSync */
-/* Description:         Processor Synchronize */
-/* Input:       none. */
-/* Output:      none. */
-/*------------------------------------------------------------------------------- */
-       .globl  ppcSync
-ppcSync:
-       sync
-       blr
-
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
@@ -1700,6 +1667,7 @@ trap_reloc:
        rlwinm  r8,r9,0,15,13
        rlwinm  r8,r8,0,17,15
        mtmsr   r8
+       mfspr   r8,dvlim
        addi    r3,r0,0x0000
        mtspr   dvlim,r3
        mfspr   r3,ivpr
@@ -1714,6 +1682,7 @@ trap_reloc:
 ..ag:  dcbf    r0,r3
        addi    r3,r3,-32
        bdnz    ..ag
+       mtspr   dvlim,r8
        sync
        mtmsr   r9
        blr