Merge with /home/wd/git/u-boot/custodian/u-boot-74xx-7xx

[platform/kernel/u-boot.git] / cpu / ppc4xx / start.S

diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 3b1586c..a96083c 100644 (file)
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -1892,11 +1892,11 @@ pll_wait:
 #endif /* CONFIG_405EP */
 
 #if defined(CONFIG_440)
-#define function_prolog(func_name)      .text; \
+#define function_prolog(func_name)     .text; \
                                        .align 2; \
                                        .globl func_name; \
                                        func_name:
-#define function_epilog(func_name)      .type func_name,@function; \
+#define function_epilog(func_name)     .type func_name,@function; \
                                        .size func_name,.-func_name
 
 /*----------------------------------------------------------------------------+
@@ -1952,13 +1952,13 @@ pll_wait:
 +----------------------------------------------------------------------------*/
        function_prolog(dcbz_area)
        rlwinm. r5,r4,0,27,31
-       rlwinm  r5,r4,27,5,31
-       beq     ..d_ra2
-       addi    r5,r5,0x0001
-..d_ra2:mtctr   r5
-..d_ag2:dcbz    r0,r3
-       addi    r3,r3,32
-       bdnz    ..d_ag2
+       rlwinm  r5,r4,27,5,31
+       beq     ..d_ra2
+       addi    r5,r5,0x0001
+..d_ra2:mtctr  r5
+..d_ag2:dcbz   r0,r3
+       addi    r3,r3,32
+       bdnz    ..d_ag2
        sync
        blr
        function_epilog(dcbz_area)
@@ -1967,26 +1967,26 @@ pll_wait:
 | dflush.  Assume 32K at vector address is cachable.
 +----------------------------------------------------------------------------*/
        function_prolog(dflush)
-       mfmsr   r9
-       rlwinm  r8,r9,0,15,13
-       rlwinm  r8,r8,0,17,15
-       mtmsr   r8
-       addi    r3,r0,0x0000
-       mtspr   dvlim,r3
-       mfspr   r3,ivpr
-       addi    r4,r0,1024
-       mtctr   r4
+       mfmsr   r9
+       rlwinm  r8,r9,0,15,13
+       rlwinm  r8,r8,0,17,15
+       mtmsr   r8
+       addi    r3,r0,0x0000
+       mtspr   dvlim,r3
+       mfspr   r3,ivpr
+       addi    r4,r0,1024
+       mtctr   r4
 ..dflush_loop:
-       lwz     r6,0x0(r3)
-       addi    r3,r3,32
-       bdnz    ..dflush_loop
-       addi    r3,r3,-32
-       mtctr   r4
-..ag:   dcbf    r0,r3
-       addi    r3,r3,-32
-       bdnz    ..ag
+       lwz     r6,0x0(r3)
+       addi    r3,r3,32
+       bdnz    ..dflush_loop
+       addi    r3,r3,-32
+       mtctr   r4
+..ag:  dcbf    r0,r3
+       addi    r3,r3,-32
+       bdnz    ..ag
        sync
-       mtmsr   r9
+       mtmsr   r9
        blr
        function_epilog(dflush)
 #endif /* CONFIG_440 */