Merge branch 'Makefile' of git://git.denx.de/u-boot-arm

[platform/kernel/u-boot.git] / cpu / ppc4xx / start.S

diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 426bf3c..97411bd 100644 (file)
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -677,7 +677,8 @@ _start:
        /* not all PPC's have internal SRAM usable as L2-cache */
 #if defined(CONFIG_440GX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_460SX)
        mtdcr   l2_cache_cfg,r0         /* Ensure L2 Cache is off */
 #endif
 
@@ -720,6 +721,19 @@ _start:
        lis     r1,0x4000               /* BAS = 8000_0000 */
        ori     r1,r1,0x4580            /* 16k */
        mtdcr   isram0_sb0cr,r1
+#elif defined(CONFIG_460SX)
+       lis     r1,0x0000               /* BAS = 0000_0000 */
+       ori     r1,r1,0x0B84            /* first 128k */
+       mtdcr   isram0_sb0cr,r1
+       lis     r1,0x0001
+       ori     r1,r1,0x0B84            /* second 128k */
+       mtdcr   isram0_sb1cr,r1
+       lis     r1, 0x0002
+       ori     r1,r1, 0x0B84           /* third 128k */
+       mtdcr   isram0_sb2cr,r1
+       lis     r1, 0x0003
+       ori     r1,r1, 0x0B84           /* fourth 128k */
+       mtdcr   isram0_sb3cr,r1
 #elif defined(CONFIG_440GP)
        ori     r1,r1,0x0380            /* 8k rw */
        mtdcr   isram0_sb0cr,r1
@@ -1415,7 +1429,8 @@ relocate_code:
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_460SX)
        /*
         * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
         * to speed up the boot process. Now this cache needs to be disabled.