mtspr srr1,r0
mtspr csrr0,r0
mtspr csrr1,r0
-
+#if defined (CONFIG_440_GX) /* NOTE: 440GX adds machine check status regs */
+ mtspr mcsrr0,r0
+ mtspr mcsrr1,r0
+ mfspr r1, mcsr
+ mtspr mcsr,r1
+#endif
/*----------------------------------------------------------------*/
/* Initialize debug */
/*----------------------------------------------------------------*/
mtspr tcr,r0 /* disable all */
mtspr esr,r0 /* clear exception syndrome register */
mtxer r0 /* clear integer exception register */
+#if !defined(CONFIG_440_GX)
lis r1,0x0002 /* set CE bit (Critical Exceptions) */
ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
mtmsr r1 /* change MSR */
+#elif !defined(CONFIG_440_EP) && !defined(CONFIG_440_GR)
+ bl __440gx_msr_set
+ b __440gx_msr_continue
+
+__440gx_msr_set:
+ lis r1, 0x0002 /* set CE bit (Critical Exceptions) */
+ ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
+ mtspr srr1,r1
+ mflr r1
+ mtspr srr0,r1
+ rfi
+__440gx_msr_continue:
+#endif
/*----------------------------------------------------------------*/
/* Debug setup -- some (not very good) ice's need an event*/
/* Setup the internal SRAM */
/*----------------------------------------------------------------*/
li r0,0
+#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
+ /* Clear Dcache to use as RAM */
+ addis r3,r0,CFG_INIT_RAM_ADDR@h
+ ori r3,r3,CFG_INIT_RAM_ADDR@l
+ addis r4,r0,CFG_INIT_RAM_END@h
+ ori r4,r4,CFG_INIT_RAM_END@l
+ rlwinm. r5,r4,0,27,31
+ rlwinm r5,r4,27,5,31
+ beq ..d_ran
+ addi r5,r5,0x0001
+..d_ran:
+ mtctr r5
+..d_ag:
+ dcbz r0,r3
+ addi r3,r3,32
+ bdnz ..d_ag
+#else
+#if defined (CONFIG_440_GX)
+ mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
+#endif
mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
li r2,0x7fff
mtdcr isram0_pmeg,r1
lis r1,0x8000 /* BAS = 8000_0000 */
+#if defined(CONFIG_440_GX)
+ ori r1,r1,0x0980 /* first 64k */
+ mtdcr isram0_sb0cr,r1
+ lis r1,0x8001
+ ori r1,r1,0x0980 /* second 64k */
+ mtdcr isram0_sb1cr,r1
+ lis r1, 0x8002
+ ori r1,r1, 0x0980 /* third 64k */
+ mtdcr isram0_sb2cr,r1
+ lis r1, 0x8003
+ ori r1,r1, 0x0980 /* fourth 64k */
+ mtdcr isram0_sb3cr,r1
+#else
ori r1,r1,0x0380 /* 8k rw */
mtdcr isram0_sb0cr,r1
+#endif
+#endif
/*----------------------------------------------------------------*/
/* Setup the stack in internal SRAM */
/* NEVER RETURNS! */
bl board_init_f /* run first part of init code (from Flash) */
-#endif /* CONFIG_405GP || CONFIG_405CR */
+#endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
+ /*----------------------------------------------------------------------- */
/*****************************************************************************/
invalidate_dcache:
addi r6,0,0x0000 /* clear GPR 6 */
/* Do loop for # of dcache congruence classes. */
+#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
+ lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
+ ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
+#else
addi r7,r0, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
+#endif
/* NOTE: dccci invalidates both */
mtctr r7 /* ways in the D cache */
..dcloop:
mtdccr r10
/* do loop for # of congruence classes. */
+#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
+ lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */
+ ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
+ lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
+ ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
+#else
addi r10,r0,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
addi r11,r0,(CFG_DCACHE_SIZE / 2) /* D cache set size - 2 way sets */
+#endif
mtctr r10
addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
add r11,r10,r11 /* add to get to other side of cache line */
*/
.globl relocate_code
relocate_code:
+#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
+ dccci 0,0 /* Invalidate data cache, now no longer our stack */
+ sync
+ addi r1,r0,0x0000 /* Tlb entry #0 */
+ tlbre r0,r1,0x0002 /* Read contents */
+ ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
+ tlbwe r0,r1,0x0002 /* Save it out */
+ isync
+#endif
mr r1, r3 /* Set new stack pointer */
mr r9, r4 /* Save copy of Init Data pointer */
mr r10, r5 /* Save copy of Destination Address */
/**************************************************************************/
#ifdef CONFIG_405EP
ppc405ep_init:
+
+#ifdef CONFIG_BUBINGA
+ /*
+ * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
+ * function) to support FPGA and NVRAM accesses below.
+ */
+
+ lis r3,GPIO0_OSRH@h /* config GPIO output select */
+ ori r3,r3,GPIO0_OSRH@l
+ lis r4,CFG_GPIO0_OSRH@h
+ ori r4,r4,CFG_GPIO0_OSRH@l
+ stw r4,0(r3)
+ lis r3,GPIO0_OSRL@h
+ ori r3,r3,GPIO0_OSRL@l
+ lis r4,CFG_GPIO0_OSRL@h
+ ori r4,r4,CFG_GPIO0_OSRL@l
+ stw r4,0(r3)
+
+ lis r3,GPIO0_ISR1H@h /* config GPIO input select */
+ ori r3,r3,GPIO0_ISR1H@l
+ lis r4,CFG_GPIO0_ISR1H@h
+ ori r4,r4,CFG_GPIO0_ISR1H@l
+ stw r4,0(r3)
+ lis r3,GPIO0_ISR1L@h
+ ori r3,r3,GPIO0_ISR1L@l
+ lis r4,CFG_GPIO0_ISR1L@h
+ ori r4,r4,CFG_GPIO0_ISR1L@l
+ stw r4,0(r3)
+
+ lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
+ ori r3,r3,GPIO0_TSRH@l
+ lis r4,CFG_GPIO0_TSRH@h
+ ori r4,r4,CFG_GPIO0_TSRH@l
+ stw r4,0(r3)
+ lis r3,GPIO0_TSRL@h
+ ori r3,r3,GPIO0_TSRL@l
+ lis r4,CFG_GPIO0_TSRL@h
+ ori r4,r4,CFG_GPIO0_TSRL@l
+ stw r4,0(r3)
+
+ lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
+ ori r3,r3,GPIO0_TCR@l
+ lis r4,CFG_GPIO0_TCR@h
+ ori r4,r4,CFG_GPIO0_TCR@l
+ stw r4,0(r3)
+
+ li r3,pb1ap /* program EBC bank 1 for RTC access */
+ mtdcr ebccfga,r3
+ lis r3,CFG_EBC_PB1AP@h
+ ori r3,r3,CFG_EBC_PB1AP@l
+ mtdcr ebccfgd,r3
+ li r3,pb1cr
+ mtdcr ebccfga,r3
+ lis r3,CFG_EBC_PB1CR@h
+ ori r3,r3,CFG_EBC_PB1CR@l
+ mtdcr ebccfgd,r3
+
+ li r3,pb1ap /* program EBC bank 1 for RTC access */
+ mtdcr ebccfga,r3
+ lis r3,CFG_EBC_PB1AP@h
+ ori r3,r3,CFG_EBC_PB1AP@l
+ mtdcr ebccfgd,r3
+ li r3,pb1cr
+ mtdcr ebccfga,r3
+ lis r3,CFG_EBC_PB1CR@h
+ ori r3,r3,CFG_EBC_PB1CR@l
+ mtdcr ebccfgd,r3
+
+ li r3,pb4ap /* program EBC bank 4 for FPGA access */
+ mtdcr ebccfga,r3
+ lis r3,CFG_EBC_PB4AP@h
+ ori r3,r3,CFG_EBC_PB4AP@l
+ mtdcr ebccfgd,r3
+ li r3,pb4cr
+ mtdcr ebccfga,r3
+ lis r3,CFG_EBC_PB4CR@h
+ ori r3,r3,CFG_EBC_PB4CR@l
+ mtdcr ebccfgd,r3
+#endif
+
+ addi r3,0,CPC0_PCI_HOST_CFG_EN
+#ifdef CONFIG_BUBINGA
/*
!-----------------------------------------------------------------------
! Check FPGA for PCI internal/external arbitration
! If board is set to internal arbitration, update cpc0_pci
!-----------------------------------------------------------------------
*/
- addi r3,0,CPC0_PCI_HOST_CFG_EN
-#ifdef CONFIG_BUBINGA405EP
addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
ori r5,r5,FPGA_REG1@l
lbz r5,0x0(r5) /* read to get PCI arb selection */
/* and CPU has been reset */
/* so skip to next section */
-#ifdef CONFIG_BUBINGA405EP
+#ifdef CONFIG_BUBINGA
/*
!-----------------------------------------------------------------------
! Read NVRAM to get value to write in PLLMR.
cmpi cr0,0,r5,1 /* See if PLL is locked */
beq pll_write
..no_pllset:
-#endif /* CONFIG_BUBINGA405EP */
+#endif /* CONFIG_BUBINGA */
addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
ori r3,r3,PLLMR0_DEFAULT@l /* */
projects / platform / kernel / u-boot.git / blobdiff