/*
- * (C) Copyright 2006 - 2007
+ * (C) Copyright 2006 - 2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (c) 2005 Cisco Systems. All rights reserved.
*/
/* define DEBUG for debugging output (obviously ;-)) */
-#if 1
+#if 0
#define DEBUG
#endif
-#include <asm/processor.h>
-#include <asm-ppc/io.h>
-#include <ppc4xx.h>
#include <common.h>
#include <pci.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <asm-ppc/io.h>
-#if defined(CONFIG_440SPE) && defined(CONFIG_PCI)
+#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
+ defined(CONFIG_PCI)
#include <asm/4xx_pcie.h>
LNKW_X8 = 0x8
};
+static int validate_endpoint(struct pci_controller *hose)
+{
+ if (hose->cfg_data == (u8 *)CFG_PCIE0_CFGBASE)
+ return (is_end_point(0));
+ else if (hose->cfg_data == (u8 *)CFG_PCIE1_CFGBASE)
+ return (is_end_point(1));
+#if CFG_PCIE_NR_PORTS > 2
+ else if (hose->cfg_data == (u8 *)CFG_PCIE2_CFGBASE)
+ return (is_end_point(2));
+#endif
+
+ return 0;
+}
+
static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
{
u8 *base = (u8*)hose->cfg_data;
base = (u8*)CFG_PCIE0_XCFGBASE;
if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE)
base = (u8*)CFG_PCIE1_XCFGBASE;
+#if CFG_PCIE_NR_PORTS > 2
if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE)
base = (u8*)CFG_PCIE2_XCFGBASE;
+#endif
}
return base;
mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
+#if CFG_PCIE_NR_PORTS > 2
mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
+#endif
}
static void pcie_dmer_enable(void)
mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
+#if CFG_PCIE_NR_PORTS > 2
mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
+#endif
}
static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
u8 *address;
*val = 0;
+ if (validate_endpoint(hose))
+ return 0; /* No upstream config access */
+
/*
* Bus numbers are relative to hose->first_busno
*/
*/
pcie_dmer_disable ();
+ debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset);
switch (len) {
case 1:
*val = in_8(hose->cfg_data + offset);
u8 *address;
+ if (validate_endpoint(hose))
+ return 0; /* No upstream config access */
+
/*
* Bus numbers are relative to hose->first_busno
*/
return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
}
+#if defined(CONFIG_440SPE)
static void ppc4xx_setup_utl(u32 port) {
volatile void *utl_base = NULL;
int err = 0;
/* SDR0_PEGPLLLCT1 reset */
- if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
+ if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000))
printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
- }
valPE0 = SDR_READ(PESDR0_RCSSET);
valPE1 = SDR_READ(PESDR1_RCSSET);
}
return 0;
}
+#endif
+
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+static void ppc4xx_setup_utl(u32 port)
+{
+ volatile void *utl_base = NULL;
+
+ /*
+ * Map UTL registers at 0x0801_n000 (4K 0xfff mask) PEGPLn_REGMSK
+ */
+ switch (port) {
+ case 0:
+ mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CFG_PCIE0_UTLBASE));
+ mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CFG_PCIE0_UTLBASE));
+ mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* BAM 11100000=4KB */
+ mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
+ break;
+
+ case 1:
+ mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CFG_PCIE0_UTLBASE));
+ mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CFG_PCIE0_UTLBASE)
+ + 0x1000);
+ mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* BAM 11100000=4KB */
+ mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
+ break;
+ }
+ utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
+
+ /*
+ * Set buffer allocations and then assert VRB and TXE.
+ */
+ out_be32(utl_base + PEUTL_PBCTL, 0x0800000c); /* PLBME, CRRE */
+ out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
+ out_be32(utl_base + PEUTL_INTR, 0x02000000);
+ out_be32(utl_base + PEUTL_OPDBSZ, 0x04000000); /* OPD = 512 Bytes */
+ out_be32(utl_base + PEUTL_PBBSZ, 0x00000000); /* Max 512 Bytes */
+ out_be32(utl_base + PEUTL_IPHBSZ, 0x02000000);
+ out_be32(utl_base + PEUTL_IPDBSZ, 0x04000000); /* IPD = 512 Bytes */
+ out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
+ out_be32(utl_base + PEUTL_PCTL, 0x80800066); /* VRB,TXE,timeout=default */
+}
+
+/*
+ * TODO: double check PCI express SDR based on the latest user manual
+ * Some registers specified here no longer exist.. has to be
+ * updated based on the final EAS spec.
+ */
+static int check_error(void)
+{
+ u32 valPE0, valPE1;
+ int err = 0;
+
+ valPE0 = SDR_READ(SDRN_PESDR_RCSSET(0));
+ valPE1 = SDR_READ(SDRN_PESDR_RCSSET(1));
+
+ /* SDR0_PExRCSSET rstgu */
+ if (!(valPE0 & PESDRx_RCSSET_RSTGU) || !(valPE1 & PESDRx_RCSSET_RSTGU)) {
+ printf("PCIE: SDR0_PExRCSSET rstgu error\n");
+ err = -1;
+ }
+
+ /* SDR0_PExRCSSET rstdl */
+ if (!(valPE0 & PESDRx_RCSSET_RSTDL) || !(valPE1 & PESDRx_RCSSET_RSTDL)) {
+ printf("PCIE: SDR0_PExRCSSET rstdl error\n");
+ err = -1;
+ }
+
+ /* SDR0_PExRCSSET rstpyn */
+ if ((valPE0 & PESDRx_RCSSET_RSTPYN) || (valPE1 & PESDRx_RCSSET_RSTPYN)) {
+ printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
+ err = -1;
+ }
+
+ /* SDR0_PExRCSSET hldplb */
+ if ((valPE0 & PESDRx_RCSSET_HLDPLB) || (valPE1 & PESDRx_RCSSET_HLDPLB)) {
+ printf("PCIE: SDR0_PExRCSSET hldplb error\n");
+ err = -1;
+ }
+
+ /* SDR0_PExRCSSET rdy */
+ if ((valPE0 & PESDRx_RCSSET_RDY) || (valPE1 & PESDRx_RCSSET_RDY)) {
+ printf("PCIE: SDR0_PExRCSSET rdy error\n");
+ err = -1;
+ }
+
+ return err;
+}
+
+/*
+ * Initialize PCI Express core as described in User Manual
+ * TODO: double check PE SDR PLL Register with the updated user manual.
+ */
+int ppc4xx_init_pcie(void)
+{
+ if (check_error())
+ return -1;
+
+ return 0;
+}
+#endif /* CONFIG_460EX */
+
+#if defined(CONFIG_405EX)
+static void ppc4xx_setup_utl(u32 port)
+{
+ u32 utl_base;
+
+ /*
+ * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK
+ */
+ switch (port) {
+ case 0:
+ mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
+ mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE);
+ mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */
+ mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
+ break;
+
+ case 1:
+ mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
+ mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE);
+ mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */
+ mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
+
+ break;
+ }
+ utl_base = (port==0) ? CFG_PCIE0_UTLBASE : CFG_PCIE1_UTLBASE;
+
+ /*
+ * Set buffer allocations and then assert VRB and TXE.
+ */
+ out_be32((u32 *)(utl_base + PEUTL_OUTTR), 0x02000000);
+ out_be32((u32 *)(utl_base + PEUTL_INTR), 0x02000000);
+ out_be32((u32 *)(utl_base + PEUTL_OPDBSZ), 0x04000000);
+ out_be32((u32 *)(utl_base + PEUTL_PBBSZ), 0x21000000);
+ out_be32((u32 *)(utl_base + PEUTL_IPHBSZ), 0x02000000);
+ out_be32((u32 *)(utl_base + PEUTL_IPDBSZ), 0x04000000);
+ out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000);
+ out_be32((u32 *)(utl_base + PEUTL_PCTL), 0x80800066);
+
+ out_be32((u32 *)(utl_base + PEUTL_PBCTL), 0x0800000c);
+ out_be32((u32 *)(utl_base + PEUTL_RCSTA),
+ in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000);
+}
+
+int ppc4xx_init_pcie(void)
+{
+ /*
+ * Nothing to do on 405EX
+ */
+ return 0;
+}
+#endif /* CONFIG_405EX */
/*
* Board-specific pcie initialization
}
#endif /* CONFIG_440SPE */
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+int __ppc4xx_init_pcie_port_hw(int port, int rootport)
+{
+ u32 val;
+ u32 utlset1;
+
+ if (rootport)
+ val = PTYPE_ROOT_PORT << 20;
+ else
+ val = PTYPE_LEGACY_ENDPOINT << 20;
+
+ if (port == 0) {
+ val |= LNKW_X1 << 12;
+ utlset1 = 0x20000000;
+ } else {
+ val |= LNKW_X4 << 12;
+ utlset1 = 0x20101101;
+ }
+
+ SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
+ SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
+ SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01210000);
+
+ switch (port) {
+ case 0:
+ SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230);
+ SDR_WRITE(PESDR0_L0DRV, 0x00000136);
+ SDR_WRITE(PESDR0_L0CLK, 0x00000006);
+
+ SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000);
+ break;
+
+ case 1:
+ SDR_WRITE(PESDR1_L0CDRCTL, 0x00003230);
+ SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230);
+ SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230);
+ SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230);
+ SDR_WRITE(PESDR1_L0DRV, 0x00000136);
+ SDR_WRITE(PESDR1_L1DRV, 0x00000136);
+ SDR_WRITE(PESDR1_L2DRV, 0x00000136);
+ SDR_WRITE(PESDR1_L3DRV, 0x00000136);
+ SDR_WRITE(PESDR1_L0CLK, 0x00000006);
+ SDR_WRITE(PESDR1_L1CLK, 0x00000006);
+ SDR_WRITE(PESDR1_L2CLK, 0x00000006);
+ SDR_WRITE(PESDR1_L3CLK, 0x00000006);
+
+ SDR_WRITE(PESDR1_PHY_CTL_RST,0x10000000);
+ break;
+ }
+
+ SDR_WRITE(SDRN_PESDR_RCSSET(port), SDR_READ(SDRN_PESDR_RCSSET(port)) |
+ (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
+
+ /* Poll for PHY reset */
+ switch (port) {
+ case 0:
+ while (!(SDR_READ(PESDR0_RSTSTA) & 0x1))
+ udelay(10);
+ break;
+ case 1:
+ while (!(SDR_READ(PESDR1_RSTSTA) & 0x1))
+ udelay(10);
+ break;
+ }
+
+ SDR_WRITE(SDRN_PESDR_RCSSET(port),
+ (SDR_READ(SDRN_PESDR_RCSSET(port)) &
+ ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
+ PESDRx_RCSSET_RSTPYN);
+
+ return 0;
+}
+#endif /* CONFIG_440SPE */
+
#if defined(CONFIG_405EX)
int __ppc4xx_init_pcie_port_hw(int port, int rootport)
{
u32 val;
- /*
- * test-only:
- * This needs some testing and perhaps changes for
- * endpoint configuration. Probably no PHY reset at all, etc.
- * sr, 2007-10-03
- */
if (rootport)
val = 0x00401000;
else
val = 0x00101000;
SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
- SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x20222222);
- SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01110000);
+ SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000);
+ SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000);
SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000);
SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003);
udelay(1000);
/* deassert the PE0_hotreset */
- SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000);
+ if (is_end_point(port))
+ SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01111000);
+ else
+ SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000);
/* poll for phy !reset */
while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000))
#endif /* CONFIG_405EX */
int ppc4xx_init_pcie_port_hw(int port, int rootport)
- __attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
+__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
/*
* We map PCI Express configuration access into the 512MB regions
* range (hangs the core upon config transaction attempts when set
* otherwise) while revA uses c_nnnn_nnnn.
*
- * For revA:
+ * For 440SPe revA:
* PCIE0: 0xc_4000_0000
* PCIE1: 0xc_8000_0000
* PCIE2: 0xc_c000_0000
*
- * For revB:
+ * For 440SPe revB:
* PCIE0: 0xd_0000_0000
* PCIE1: 0xd_2000_0000
* PCIE2: 0xd_4000_0000
* For 405EX:
* PCIE0: 0xa000_0000
* PCIE1: 0xc000_0000
+ *
+ * For 460EX/GT:
+ * PCIE0: 0xd_0000_0000
+ * PCIE1: 0xd_2000_0000
*/
static inline u64 ppc4xx_get_cfgaddr(int port)
{
}
}
#endif
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ if (port == 0)
+ return 0x0000000d00000000ULL;
+ else
+ return 0x0000000d20000000ULL;
+#endif
}
/*
u32 low, high;
if (!core_init) {
- ++core_init;
if (ppc4xx_init_pcie())
return -1;
+ ++core_init;
}
/*
* We map PCI Express configuration access into the 512MB regions
*/
addr = ppc4xx_get_cfgaddr(port);
- low = (u32)(addr & 0x00000000ffffffff);
- high = (u32)(addr >> 32);
+ low = U64_TO_U32_LOW(addr);
+ high = U64_TO_U32_HIGH(addr);
switch (port) {
case 0:
mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low);
mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
break;
+#if CFG_PCIE_NR_PORTS > 2
case 2:
mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low);
mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
break;
+#endif
}
/*
rmbase = (u32 *)CFG_PCIE1_CFGBASE;
hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
break;
+#if CFG_PCIE_NR_PORTS > 2
case 2:
mbase = (u32 *)CFG_PCIE2_XCFGBASE;
rmbase = (u32 *)CFG_PCIE2_CFGBASE;
hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
break;
+#endif
}
/*
switch (port) {
case 0:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
port * CFG_PCIE_MEMSIZE);
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0)));
break;
case 1:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
port * CFG_PCIE_MEMSIZE);
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)),
mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1)));
break;
+#if CFG_PCIE_NR_PORTS > 2
case 2:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
port * CFG_PCIE_MEMSIZE);
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)),
mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2)));
break;
+#endif
}
/* Set up 16GB inbound memory window at 0 */
out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
out_le32(mbase + PECFG_PIM0LAL, 0);
out_le32(mbase + PECFG_PIM0LAH, 0);
- out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
- out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
+ out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
+ out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
out_le32(mbase + PECFG_PIMEN, 0x1);
/* Enable I/O, Mem, and Busmaster cycles */
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
/* Set Device and Vendor Id */
- switch (port) {
- case 0:
- out_le16(mbase + 0x200, 0xaaa0);
- out_le16(mbase + 0x202, 0xbed0);
- break;
- case 1:
- out_le16(mbase + 0x200, 0xaaa1);
- out_le16(mbase + 0x202, 0xbed1);
- break;
- case 2:
- out_le16(mbase + 0x200, 0xaaa2);
- out_le16(mbase + 0x202, 0xbed2);
- break;
- default:
- out_le16(mbase + 0x200, 0xaaa3);
- out_le16(mbase + 0x202, 0xbed3);
- }
+ out_le16(mbase + 0x200, 0xaaa0 + port);
+ out_le16(mbase + 0x202, 0xbed0 + port);
/* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
out_le32(mbase + 0x208, 0x06040001);
- printf("PCIE:%d successfully set as rootpoint\n", port);
+ printf("PCIE%d: successfully set as root-complex\n", port);
}
int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
mbase = (u32 *)CFG_PCIE1_XCFGBASE;
hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
break;
+#if defined(CFG_PCIE2_CFGBASE)
case 2:
mbase = (u32 *)CFG_PCIE2_XCFGBASE;
hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
break;
+#endif
}
/*
switch (port) {
case 0:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
port * CFG_PCIE_MEMSIZE);
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
~(CFG_PCIE_MEMSIZE - 1) | 3);
break;
case 1:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
port * CFG_PCIE_MEMSIZE);
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
~(CFG_PCIE_MEMSIZE - 1) | 3);
break;
+#if CFG_PCIE_NR_PORTS > 2
case 2:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
port * CFG_PCIE_MEMSIZE);
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
~(CFG_PCIE_MEMSIZE - 1) | 3);
break;
+#endif
}
- /* Set up 16GB inbound memory window at 0 */
+ /* Set up 64MB inbound memory window at 0 */
out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
- out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
- out_le32(mbase + PECFG_BAR0LMPA, 0);
- out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
- out_le32(mbase + PECFG_PIM0LAH, 0x00000004); /* pointing to SRAM */
+
+ out_le32(mbase + PECFG_PIM01SAH, 0xffffffff);
+ out_le32(mbase + PECFG_PIM01SAL, 0xfc000000);
+
+ /* Setup BAR0 */
+ out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffff);
+ out_le32(mbase + PECFG_BAR0LMPA, 0xfc000000 | PCI_BASE_ADDRESS_MEM_TYPE_64);
+
+ /* Disable BAR1 & BAR2 */
+ out_le32(mbase + PECFG_BAR1MPA, 0);
+ out_le32(mbase + PECFG_BAR2HMPA, 0);
+ out_le32(mbase + PECFG_BAR2LMPA, 0);
+
+ out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CFG_PCIE_INBOUND_BASE));
+ out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CFG_PCIE_INBOUND_BASE));
out_le32(mbase + PECFG_PIMEN, 0x1);
/* Enable I/O, Mem, and Busmaster cycles */
out_le16((u16 *)(mbase + PCI_COMMAND),
in_le16((u16 *)(mbase + PCI_COMMAND)) |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
- out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */
- out_le16(mbase + 0x202,0xfeed); /* Setting device ID */
+ out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */
+ out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */
+
+ /* Set Class Code to Processor/PPC */
+ out_le32(mbase + 0x208, 0x0b200001);
attempts = 10;
while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) {
mdelay(1000);
}
- printf("PCIE:%d successfully set as endpoint\n",port);
+ printf("PCIE%d: successfully set as endpoint\n", port);
return 0;
}
projects / platform / kernel / u-boot.git / blobdiff