Merge with git://www.denx.de/git/u-boot.git

[platform/kernel/u-boot.git] / cpu / ppc4xx / 4xx_enet.c

diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index cf56581..cc8e734 100644 (file)
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -94,9 +94,9 @@
  * network support enabled.
  * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
  */
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
+#if defined(CONFIG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
 
-#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
+#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
 #error "CONFIG_MII has to be defined!"
 #endif
 
@@ -339,29 +339,41 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
 {
        unsigned long zmiifer=0x0;
+       unsigned long pfc1;
 
-       /*
-        * Right now only 2*RGMII is supported. Please extend when needed.
-        * sr - 2006-08-29
-        */
-       switch (1) {
-       case 0:
+       mfsdr(sdr_pfc1, pfc1);
+       pfc1 &= SDR0_PFC1_SELECT_MASK;
+
+       switch (pfc1) {
+       case SDR0_PFC1_SELECT_CONFIG_2:
                /* 1 x GMII port */
                out32 (ZMII_FER, 0x00);
                out32 (RGMII_FER, 0x00000037);
                bis->bi_phymode[0] = BI_PHYMODE_GMII;
                bis->bi_phymode[1] = BI_PHYMODE_NONE;
                break;
-       case 1:
+       case SDR0_PFC1_SELECT_CONFIG_4:
                /* 2 x RGMII ports */
                out32 (ZMII_FER, 0x00);
                out32 (RGMII_FER, 0x00000055);
                bis->bi_phymode[0] = BI_PHYMODE_RGMII;
                bis->bi_phymode[1] = BI_PHYMODE_RGMII;
                break;
-       case 2:
+       case SDR0_PFC1_SELECT_CONFIG_6:
                /* 2 x SMII ports */
-
+               out32 (ZMII_FER,
+                      ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
+                      ((ZMII_FER_SMII) << ZMII_FER_V(1)));
+               out32 (RGMII_FER, 0x00000000);
+               bis->bi_phymode[0] = BI_PHYMODE_SMII;
+               bis->bi_phymode[1] = BI_PHYMODE_SMII;
+               break;
+       case SDR0_PFC1_SELECT_CONFIG_1_2:
+               /* only 1 x MII supported */
+               out32 (ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
+               out32 (RGMII_FER, 0x00000000);
+               bis->bi_phymode[0] = BI_PHYMODE_MII;
+               bis->bi_phymode[1] = BI_PHYMODE_NONE;
                break;
        default:
                break;
@@ -1403,10 +1415,8 @@ static void enet_rcv (struct eth_device *dev, unsigned long malisr)
                        if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
                            || (loop_count >= NUM_RX_BUFF))
                                break;
+
                        loop_count++;
-                       hw_p->rx_slot++;
-                       if (NUM_RX_BUFF == hw_p->rx_slot)
-                               hw_p->rx_slot = 0;
                        handled++;
                        data_len = (unsigned long) hw_p->rx[i].data_len;        /* Get len */
                        if (data_len) {
@@ -1456,6 +1466,10 @@ static void enet_rcv (struct eth_device *dev, unsigned long malisr)
                                if (NUM_RX_BUFF == hw_p->rx_i_index)
                                        hw_p->rx_i_index = 0;
 
+                               hw_p->rx_slot++;
+                               if (NUM_RX_BUFF == hw_p->rx_slot)
+                                       hw_p->rx_slot = 0;
+
                                /*  AS.HARNOIS
                                 * free receive buffer only when
                                 * buffer has been handled (eth_rx)
@@ -1671,7 +1685,7 @@ int ppc_4xx_eth_initialize (bd_t * bis)
 #endif
 
 #if defined(CONFIG_NET_MULTI)
-#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
                miiphy_register (dev->name,
                                 emac4xx_miiphy_read, emac4xx_miiphy_write);
 #endif
@@ -1712,7 +1726,7 @@ int eth_rx(void)
 
 int emac4xx_miiphy_initialize (bd_t * bis)
 {
-#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
        miiphy_register ("ppc_4xx_eth0",
                         emac4xx_miiphy_read, emac4xx_miiphy_write);
 #endif
@@ -1721,4 +1735,4 @@ int emac4xx_miiphy_initialize (bd_t * bis)
 }
 #endif /* !defined(CONFIG_NET_MULTI) */
 
-#endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */
+#endif