#include <common.h>
-#if defined(CFG_NIOS_EPCSBASE)
+#if defined(CONFIG_SYS_NIOS_EPCSBASE)
#include <command.h>
-#include <nios2.h>
+#include <asm/io.h>
#include <nios2-io.h>
#include <nios2-epcs.h>
"epcs write addr offset count\n"\
" - write count bytes to offset from addr.\n"\
"epcs verify addr offset count\n"\
- " - verify count bytes at offset from addr.\n"
+ " - verify count bytes at offset from addr."
/*-----------------------------------------------------------------------*/
*/
#define EPCS_TIMEOUT 100 /* 100 msec timeout */
-static nios_spi_t *epcs =
- (nios_spi_t *)CACHE_BYPASS(CFG_NIOS_EPCSBASE);
+static nios_spi_t *epcs = (nios_spi_t *)CONFIG_SYS_NIOS_EPCSBASE;
/***********************************************************************
* Device access
static int epcs_cs (int assert)
{
ulong start;
+ unsigned tmp;
+
if (assert) {
- epcs->control |= NIOS_SPI_SSO;
+ tmp = readl (&epcs->control);
+ writel (tmp | NIOS_SPI_SSO, &epcs->control);
} else {
/* Let all bits shift out */
start = get_timer (0);
- while ((epcs->status & NIOS_SPI_TMT) == 0)
+ while ((readl (&epcs->status) & NIOS_SPI_TMT) == 0)
if (get_timer (start) > EPCS_TIMEOUT)
return (-1);
- epcs->control &= ~NIOS_SPI_SSO;
+ tmp = readl (&epcs->control);
+ writel (tmp & ~NIOS_SPI_SSO, &epcs->control);
}
return (0);
}
ulong start;
start = get_timer (0);
- while ((epcs->status & NIOS_SPI_TRDY) == 0)
+ while ((readl (&epcs->status) & NIOS_SPI_TRDY) == 0)
if (get_timer (start) > EPCS_TIMEOUT)
return (-1);
- epcs->txdata = c;
+ writel (c, &epcs->txdata);
return (0);
}
ulong start;
start = get_timer (0);
- while ((epcs->status & NIOS_SPI_RRDY) == 0)
+ while ((readl (&epcs->status) & NIOS_SPI_RRDY) == 0)
if (get_timer (start) > EPCS_TIMEOUT)
return (-1);
- return (epcs->rxdata);
+ return (readl (&epcs->rxdata));
}
static unsigned char bitrev[] = {
static struct epcs_devinfo_t devinfo[] = {
{ "EPCS1 ", 0x10, 17, 4, 15, 8, 0x0c },
{ "EPCS4 ", 0x12, 19, 8, 16, 8, 0x1c },
+ { "EPCS16", 0x14, 21, 32, 16, 8, 0x1c },
+ { "EPCS64", 0x16, 23,128, 16, 8, 0x1c },
{ 0, 0, 0, 0, 0, 0 }
};
+int epcs_reset (void)
+{
+ /* When booting from an epcs controller, the epcs bootrom
+ * code may leave the slave select in an asserted state.
+ * This causes two problems: (1) The initial epcs access
+ * will fail -- not a big deal, and (2) a software reset
+ * will cause the bootrom code to hang since it does not
+ * ensure the select is negated prior to first access -- a
+ * big deal. Here we just negate chip select and everything
+ * gets better :-)
+ */
+ epcs_cs (0); /* Negate chip select */
+ return (0);
+}
+
epcs_devinfo_t *epcs_dev_find (void)
{
unsigned char buf[4];
}
/* Sector info */
- for (i=0; i<dev->num_sects; i++) {
+ for (i=0; (i < dev->num_sects) && (argc > 1); i++) {
erased = epcs_sect_erased (i, &tmp, dev);
- printf (" %d: %06x ",
+ if ((i & 0x03) == 0) printf ("\n");
+ printf ("%4d: %07x ",
i, i*(1<<dev->sz_sect) );
if (erased)
- printf ("erased\n");
+ printf ("E ");
else
- printf ("data @ 0x%06x\n", tmp);
+ printf (" ");
}
+ printf ("\n");
return;
}