* Add variable CPU clock for MPC859/866 systems (so far only TQM866M):

[platform/kernel/u-boot.git] / cpu / mpc8xx / cpu_init.c

diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c
index abe6209..c7716dd 100644 (file)
--- a/cpu/mpc8xx/cpu_init.c
+++ b/cpu/mpc8xx/cpu_init.c
@@ -42,8 +42,11 @@ void cpu_init_f (volatile immap_t * immr)
 {
 #ifndef CONFIG_MBX
        volatile memctl8xx_t *memctl = &immr->im_memctl;
-       ulong reg;
+# ifdef CFG_PLPRCR
+       ulong mfmask;
+# endif
 #endif
+       ulong reg;
 
        /* SYPCR - contains watchdog control (11-9) */
 
@@ -54,9 +57,11 @@ void cpu_init_f (volatile immap_t * immr)
 #endif /* CONFIG_WATCHDOG */
 
        /* SIUMCR - contains debug pin configuration (11-6) */
-
+#ifndef CONFIG_SVM_SC8xx
        immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR;
-
+#else
+       immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
+#endif
        /* initialize timebase status and control register (11-26) */
        /* unlock TBSCRK */
 
@@ -68,6 +73,14 @@ void cpu_init_f (volatile immap_t * immr)
        immr->im_sitk.sitk_piscrk = KAPWR_KEY;
        immr->im_sit.sit_piscr = CFG_PISCR;
 
+       /* System integration timers. Don't change EBDF! (15-27) */
+
+       immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
+       reg = immr->im_clkrst.car_sccr;
+       reg &= SCCR_MASK;
+       reg |= CFG_SCCR;
+       immr->im_clkrst.car_sccr = reg;
+
        /* PLL (CPU clock) settings (15-30) */
 
        immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
@@ -76,25 +89,26 @@ void cpu_init_f (volatile immap_t * immr)
 
        /* If CFG_PLPRCR (set in the various *_config.h files) tries to
         * set the MF field, then just copy CFG_PLPRCR over car_plprcr,
-        * otherwise OR in CFG_PLPRCR so we do not change the currentMF
+        * otherwise OR in CFG_PLPRCR so we do not change the current MF
         * field value.
+        *
+        * For newer (starting MPC866) chips PLPRCR layout is different.
         */
-#if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0)
-       reg = CFG_PLPRCR;                       /* reset control bits   */
-#else
-       reg = immr->im_clkrst.car_plprcr;
-       reg &= PLPRCR_MF_MSK;                   /* isolate MF field */
-       reg |= CFG_PLPRCR;                      /* reset control bits   */
-#endif
+#ifdef CFG_PLPRCR
+       if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK)
+          mfmask = PLPRCR_MFACT_MSK;
+       else
+          mfmask = PLPRCR_MF_MSK;
+
+       if ((CFG_PLPRCR & mfmask) != 0)
+          reg = CFG_PLPRCR;                    /* reset control bits   */
+       else {
+          reg = immr->im_clkrst.car_plprcr;
+          reg &= mfmask;                       /* isolate MF-related fields */
+          reg |= CFG_PLPRCR;                   /* reset control bits   */
+       }
        immr->im_clkrst.car_plprcr = reg;
-
-       /* System integration timers. Don't change EBDF! (15-27) */
-
-       immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
-       reg = immr->im_clkrst.car_sccr;
-       reg &= SCCR_MASK;
-       reg |= CFG_SCCR;
-       immr->im_clkrst.car_sccr = reg;
+#endif
 
        /*
         * Memory Controller:
@@ -130,7 +144,8 @@ void cpu_init_f (volatile immap_t * immr)
         *  I owe him a free beer. - wd]
         */
 
-#if defined(CONFIG_GTH)                || \
+#if defined(CONFIG_ADDERII)    || \
+    defined(CONFIG_GTH)                || \
     defined(CONFIG_HERMES)     || \
     defined(CONFIG_ICU862)     || \
     defined(CONFIG_IP860)      || \
@@ -142,8 +157,7 @@ void cpu_init_f (volatile immap_t * immr)
     defined(CONFIG_R360MPI)    || \
     defined(CONFIG_RPXCLASSIC) || \
     defined(CONFIG_RPXLITE)    || \
-    defined(CONFIG_SPD823TS)   || \
-   (defined(CONFIG_MPC860T) && defined(CONFIG_FADS))
+    defined(CONFIG_SPD823TS)
 
        memctl->memc_br0 = CFG_BR0_PRELIM;
 #endif