#include <i2c.h>
#include <spd.h>
#include <asm/mmu.h>
-
+#include <asm/fsl_law.h>
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void dma_init(void);
caslat -= 1;
else if (busfreq > max_data_rate) {
printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
- busfreq, max_data_rate);
+ busfreq, max_data_rate);
return 0;
}
}
/*
* Sneak in some Extended Refresh Recovery.
*/
- ddr->ext_refrec = (trfc_high << 16);
- debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
+ ddr->timing_cfg_3 = (trfc_high << 16);
+ debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
ddr->timing_cfg_1 =
(0
spd_eeprom_t spd1,spd2;
volatile ccsr_ddr_t *ddr;
unsigned sdram_cfg_1;
- unsigned char sdram_type, mem_type, config, mod_attr;
+ unsigned char sdram_type, mem_type, mod_attr;
unsigned char d_init;
unsigned int no_dimm1=0, no_dimm2=0;
printf("No memory modules found for DDR controller %d!!\n", ddr_num);
return 0;
} else {
+
+#if defined(CONFIG_DDR_ECC)
+ unsigned char config;
+#endif
mem_type = no_dimm2 ? spd1.mem_type : spd2.mem_type;
/*
int memsize_ddr1_dimm2 = 0;
int memsize_ddr1 = 0;
unsigned int law_size_ddr1;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
#ifdef CONFIG_DDR_INTERLEAVE
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
#endif
/*
* Set up LAWBAR for DDR 1 space.
*/
- mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
- mcm->lawar1 = (LAWAR_EN
- | LAWAR_TRGT_IF_DDR_INTERLEAVED
- | (LAWAR_SIZE & law_size_interleaved));
- debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
- debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
+#ifdef CONFIG_FSL_LAW
+ set_next_law(CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV);
+#endif
debug("Interleaved memory size is 0x%08lx\n", memsize_total);
-#ifdef CONFIG_DDR_INTERLEAVE
#if (CFG_PAGE_INTERLEAVING == 1)
printf("Page ");
#elif (CFG_BANK_INTERLEAVING == 1)
#else
printf("Cache-line ");
#endif
-#endif
printf("Interleaved");
return memsize_total * 1024 * 1024;
} else {
/*
* Set up LAWBAR for DDR 1 space.
*/
- mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
- mcm->lawar1 = (LAWAR_EN
- | LAWAR_TRGT_IF_DDR1
- | (LAWAR_SIZE & law_size_ddr1));
- debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
- debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
+#ifdef CONFIG_FSL_LAW
+ set_next_law(CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1);
+#endif
}
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
/*
* Set up LAWBAR for DDR 2 space.
*/
- if (ddr1_enabled)
- mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12)
- & 0xfffff);
- else
- mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
-
- mcm->lawar8 = (LAWAR_EN
- | LAWAR_TRGT_IF_DDR2
- | (LAWAR_SIZE & law_size_ddr2));
- debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
- debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
+#ifdef CONFIG_FSL_LAW
+ set_next_law(
+ (ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE),
+ law_size_ddr2, LAW_TRGT_IF_DDR_2);
+#endif
}
debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2);