Merge branch 'master' of git://git.denx.de/u-boot-arm

[platform/kernel/u-boot.git] / cpu / mpc86xx / ddr-8641.c

diff --git a/cpu/mpc86xx/ddr-8641.c b/cpu/mpc86xx/ddr-8641.c
index 932ef22..b8f2c93 100644 (file)
--- a/cpu/mpc86xx/ddr-8641.c
+++ b/cpu/mpc86xx/ddr-8641.c
@@ -22,10 +22,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 
        switch (ctrl_num) {
        case 0:
-               ddr = (void *)CFG_MPC86xx_DDR_ADDR;
+               ddr = (void *)CONFIG_SYS_MPC86xx_DDR_ADDR;
                break;
        case 1:
-               ddr = (void *)CFG_MPC86xx_DDR2_ADDR;
+               ddr = (void *)CONFIG_SYS_MPC86xx_DDR2_ADDR;
                break;
        default:
                printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
@@ -35,7 +35,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
                if (i == 0) {
                        out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
-                       out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
                        out_be32(&ddr->cs0_config, regs->cs[i].config);
 
                } else if (i == 1) {
@@ -57,7 +56,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
        out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
        out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
-       out_be32(&ddr->sdram_mode_1, regs->ddr_sdram_mode);
+       out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
        out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
        out_be32(&ddr->sdram_mode_cntl, regs->ddr_sdram_md_cntl);
        out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
@@ -75,7 +74,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        udelay(200);
        asm volatile("sync;isync");
 
-       out_be32(&ddr->sdram_cfg_1, regs->ddr_sdram_cfg);
+       out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
 
        /*
         * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done