Merge branch 'master' of git://git.denx.de/u-boot-blackfin

[platform/kernel/u-boot.git] / cpu / mpc85xx / start.S

diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index c9e91a9..b3cb56a 100644 (file)
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004, 2007-2009 Freescale Semiconductor.
+ * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
  * Copyright (C) 2003  Motorola,Inc.
  *
  * See file CREDITS for list of people who contributed to this
@@ -51,7 +51,7 @@
 /*
  * Set up GOT: Global Offset Table
  *
- * Use r14 to access the GOT
+ * Use r12 to access the GOT
  */
        START_GOT
        GOT_ENTRY(_GOT2_TABLE_)
@@ -102,13 +102,47 @@ _start_e500:
         *
         */
 
-       lis     r2,L1CSR0_CPE@H /* enable parity */
-       ori     r2,r2,L1CSR0_DCE
-       mtspr   L1CSR0,r2       /* enable L1 Dcache */
+#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
+       /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
+       li      r2,(32 + 0)
+       mtspr   L1CSR2,r2
+#endif
+
+       /* Enable/invalidate the I-Cache */
+       lis     r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
+       ori     r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
+       mtspr   SPRN_L1CSR1,r2
+1:
+       mfspr   r3,SPRN_L1CSR1
+       and.    r1,r3,r2
+       bne     1b
+
+       lis     r3,(L1CSR1_CPE|L1CSR1_ICE)@h
+       ori     r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
+       mtspr   SPRN_L1CSR1,r3
        isync
-       mtspr   L1CSR1,r2       /* enable L1 Icache */
+2:
+       mfspr   r3,SPRN_L1CSR1
+       andi.   r1,r3,L1CSR1_ICE@l
+       beq     2b
+
+       /* Enable/invalidate the D-Cache */
+       lis     r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
+       ori     r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
+       mtspr   SPRN_L1CSR0,r2
+1:
+       mfspr   r3,SPRN_L1CSR0
+       and.    r1,r3,r2
+       bne     1b
+
+       lis     r3,(L1CSR0_CPE|L1CSR0_DCE)@h
+       ori     r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
+       mtspr   SPRN_L1CSR0,r3
        isync
-       msync
+2:
+       mfspr   r3,SPRN_L1CSR0
+       andi.   r1,r3,L1CSR0_DCE@l
+       beq     2b
 
        /* Setup interrupt vectors */
        lis     r1,TEXT_BASE@h
@@ -174,13 +208,21 @@ _start_e500:
 
 #ifndef CONFIG_E500MC
        li      r0,(HID1_ASTME|HID1_ABE)@l      /* Addr streaming & broadcast */
+       mfspr   r3,PVR
+       andi.   r3,r3, 0xff
+       cmpwi   r3,0x50@l       /* if we are rev 5.0 or greater set MBDD */
+       blt 1f
+       /* Set MBDD bit also */
+       ori r0, r0, HID1_MBDD@l
+1:
        mtspr   HID1,r0
 #endif
 
        /* Enable Branch Prediction */
 #if defined(CONFIG_BTB)
-       li      r0,0x201                /* BBFI = 1, BPEN = 1 */
-       mtspr   BUCSR,r0
+       lis     r0,BUCSR_ENABLE@h
+       ori     r0,r0,BUCSR_ENABLE@l
+       mtspr   SPRN_BUCSR,r0
 #endif
 
 #if defined(CONFIG_SYS_INIT_DBCR)
@@ -409,28 +451,15 @@ Alignment:
        mfspr   r5,DSISR
        stw     r5,_DSISR(r21)
        addi    r3,r1,STACK_FRAME_OVERHEAD
-       li      r20,MSR_KERNEL
-       rlwimi  r20,r23,0,16,16         /* copy EE bit from saved MSR */
-       lwz     r6,GOT(transfer_to_handler)
-       mtlr    r6
-       blrl
-.L_Alignment:
-       .long   AlignmentException - _start + _START_OFFSET
-       .long   int_return - _start + _START_OFFSET
+       EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
 
 /* Program check exception */
        . = 0x0700
 ProgramCheck:
        EXCEPTION_PROLOG(SRR0, SRR1)
        addi    r3,r1,STACK_FRAME_OVERHEAD
-       li      r20,MSR_KERNEL
-       rlwimi  r20,r23,0,16,16         /* copy EE bit from saved MSR */
-       lwz     r6,GOT(transfer_to_handler)
-       mtlr    r6
-       blrl
-.L_ProgramCheck:
-       .long   ProgramCheckException - _start + _START_OFFSET
-       .long   int_return - _start + _START_OFFSET
+       EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
+               MSR_KERNEL, COPY_EE)
 
        /* No FPU on MPC85xx.  This exception is not supposed to happen.
        */
@@ -878,6 +907,7 @@ relocate_code:
        mr      r9,r4           /* Save copy of Init Data pointer       */
        mr      r10,r5          /* Save copy of Destination Address     */
 
+       GET_GOT
        mr      r3,r5                           /* Destination Address  */
        lis     r4,CONFIG_SYS_MONITOR_BASE@h            /* Source      Address  */
        ori     r4,r4,CONFIG_SYS_MONITOR_BASE@l
@@ -895,7 +925,7 @@ relocate_code:
        sub     r15,r10,r4
 
        /* First our own GOT */
-       add     r14,r14,r15
+       add     r12,r12,r15
        /* the the one used by the C code */
        add     r30,r30,r15
 
@@ -965,7 +995,7 @@ relocate_code:
 in_ram:
 
        /*
-        * Relocation Function, r14 point to got2+0x8000
+        * Relocation Function, r12 point to got2+0x8000
         *
         * Adjust got2 pointers, no need to check for 0, this code
         * already puts a few entries in the table.
@@ -977,15 +1007,17 @@ in_ram:
        sub     r11,r3,r11
        addi    r3,r3,-4
 1:     lwzu    r0,4(r3)
+       cmpwi   r0,0
+       beq-    2f
        add     r0,r0,r11
        stw     r0,0(r3)
-       bdnz    1b
+2:     bdnz    1b
 
        /*
         * Now adjust the fixups and the pointers to the fixups
         * in case we need to move ourselves again.
         */
-2:     li      r0,__fixup_entries@sectoff@l
+       li      r0,__fixup_entries@sectoff@l
        lwz     r3,GOT(_FIXUP_TABLE_)
        cmpwi   r0,0
        mtctr   r0
@@ -1029,6 +1061,8 @@ clear_bss:
         */
        .globl  trap_init
 trap_init:
+       mflr    r4                      /* save link register           */
+       GET_GOT
        lwz     r7,GOT(_start_of_vectors)
        lwz     r8,GOT(_end_of_vectors)
 
@@ -1036,8 +1070,6 @@ trap_init:
 
        cmplw   0,r7,r8
        bgelr                           /* return if r7>=r8 - just in case */
-
-       mflr    r4                      /* save link register           */
 1:
        lwz     r0,0(r7)
        stw     r0,0(r9)
@@ -1081,20 +1113,6 @@ trap_init:
        mtlr    r4                      /* restore link register        */
        blr
 
-       /*
-        * Function: relocate entries for one exception vector
-        */
-trap_reloc:
-       lwz     r0,0(r7)                /* hdlr ...                     */
-       add     r0,r0,r3                /*  ... += dest_addr            */
-       stw     r0,0(r7)
-
-       lwz     r0,4(r7)                /* int_return ...               */
-       add     r0,r0,r3                /*  ... += dest_addr            */
-       stw     r0,4(r7)
-
-       blr
-
 .globl unlock_ram_in_cache
 unlock_ram_in_cache:
        /* invalidate the INIT_RAM section */