/*
* Sneak in some Extended Refresh Recovery.
*/
- ddr->ext_refrec = (trfc_high << 16);
- debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
+ ddr->timing_cfg_3 = (trfc_high << 16);
+ debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
ddr->timing_cfg_1 =
(0
*/
#ifdef CONFIG_FSL_LAW
- set_law(1, CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR);
+ set_next_law(CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR);
#endif
/*