Merge branch 'master' of git://git.denx.de/u-boot-blackfin

[platform/kernel/u-boot.git] / cpu / mpc85xx / release.S

diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index a1ae78a..0b5b9da 100644 (file)
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
  * Kumar Gala <kumar.gala@freescale.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -57,11 +57,19 @@ __secondary_start_page:
 
 #ifndef CONFIG_E500MC
        li      r3,(HID1_ASTME|HID1_ABE)@l      /* Addr streaming & broadcast */
+       mfspr   r0,PVR
+       andi.   r0,r0,0xff
+       cmpwi   r0,0x50@l       /* if we are rev 5.0 or greater set MBDD */
+       blt 1f
+       /* Set MBDD bit also */
+       ori r3, r3, HID1_MBDD@l
+1:
        mtspr   SPRN_HID1,r3
 #endif
 
        /* Enable branch prediction */
-       li      r3,0x201
+       lis     r3,BUCSR_ENABLE@h
+       ori     r3,r3,BUCSR_ENABLE@l
        mtspr   SPRN_BUCSR,r3
 
        /* Ensure TB is 0 */
@@ -70,18 +78,40 @@ __secondary_start_page:
        mttbu   r3
 
        /* Enable/invalidate the I-Cache */
-       mfspr   r0,SPRN_L1CSR1
-       ori     r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
-       mtspr   SPRN_L1CSR1,r0
+       lis     r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
+       ori     r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
+       mtspr   SPRN_L1CSR1,r2
+1:
+       mfspr   r3,SPRN_L1CSR1
+       and.    r1,r3,r2
+       bne     1b
+
+       lis     r3,(L1CSR1_CPE|L1CSR1_ICE)@h
+       ori     r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
+       mtspr   SPRN_L1CSR1,r3
        isync
+2:
+       mfspr   r3,SPRN_L1CSR1
+       andi.   r1,r3,L1CSR1_ICE@l
+       beq     2b
 
        /* Enable/invalidate the D-Cache */
-       mfspr   r0,SPRN_L1CSR0
-       ori     r0,r0,(L1CSR0_DCFI|L1CSR0_DCE)
-       msync
-       isync
-       mtspr   SPRN_L1CSR0,r0
+       lis     r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
+       ori     r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
+       mtspr   SPRN_L1CSR0,r2
+1:
+       mfspr   r3,SPRN_L1CSR0
+       and.    r1,r3,r2
+       bne     1b
+
+       lis     r3,(L1CSR0_CPE|L1CSR0_DCE)@h
+       ori     r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
+       mtspr   SPRN_L1CSR0,r3
        isync
+2:
+       mfspr   r3,SPRN_L1CSR0
+       andi.   r1,r3,L1CSR0_DCE@l
+       beq     2b
 
 #define toreset(x) (x - __secondary_start_page + 0xfffff000)
 
@@ -99,21 +129,38 @@ __secondary_start_page:
        slwi    r8,r4,5
        add     r10,r3,r8
 
+#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
+       /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
+       slwi    r8,r4,1
+       addi    r8,r8,32
+       mtspr   L1CSR2,r8
+#endif
+
 #ifdef CONFIG_BACKSIDE_L2_CACHE
        /* Enable/invalidate the L2 cache */
        msync
-       lis     r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
-       ori     r3,r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
-       mtspr   SPRN_L2CSR0,r3
+       lis     r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
+       ori     r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
+       mtspr   SPRN_L2CSR0,r2
 1:
        mfspr   r3,SPRN_L2CSR0
-       andis.  r1,r3,L2CSR0_L2FI@h
+       and.    r1,r3,r2
        bne     1b
 
+#ifdef CONFIG_SYS_CACHE_STASHING
+       /* set stash id to (coreID) * 2 + 32 + L2 (1) */
+       addi    r3,r8,1
+       mtspr   SPRN_L2CSR1,r3
+#endif
+
        lis     r3,CONFIG_SYS_INIT_L2CSR0@h
        ori     r3,r3,CONFIG_SYS_INIT_L2CSR0@l
        mtspr   SPRN_L2CSR0,r3
        isync
+2:
+       mfspr   r3,SPRN_L2CSR0
+       andis.  r1,r3,L2CSR0_L2E@h
+       beq     2b
 #endif
 
 #define EPAPR_MAGIC            (0x45504150)
@@ -149,8 +196,8 @@ __secondary_start_page:
        lis     r11,(MAS1_VALID|MAS1_IPROT)@h
        ori     r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
        mtspr   SPRN_MAS1,r11
-       oris    r11,r13,(MAS2_I)@h
-       ori     r11,r13,(MAS2_I)@l
+       oris    r11,r13,(MAS2_I|MAS2_G)@h
+       ori     r11,r13,(MAS2_I|MAS2_G)@l
        mtspr   SPRN_MAS2,r11
        oris    r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
        ori     r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l