Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx

[platform/kernel/u-boot.git] / cpu / mpc85xx / cpu_init.c

diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 4e2bfe7..736aef1 100644 (file)
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -33,6 +33,7 @@
 #include <asm/io.h>
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
+#include "mp.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -127,12 +128,12 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 /* We run cpu_init_early_f in AS = 1 */
 void cpu_init_early_f(void)
 {
-       set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR,
+       set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                1, 0, BOOKE_PAGESZ_4K, 0);
 
        /* set up CCSR if we want it moved */
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS)
        {
                u32 temp;
 
@@ -141,35 +142,21 @@ void cpu_init_early_f(void)
                        1, 1, BOOKE_PAGESZ_4K, 0);
 
                temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT);
-               out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR >> 12);
+               out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_PHYS >> 12);
 
                temp = in_be32((volatile u32 *)CFG_CCSRBAR);
        }
 #endif
 
+       /* Pointer is writable since we allocated a register for it */
+       gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+
+       /* Clear initial global data */
+       memset ((void *) gd, 0, sizeof (gd_t));
+
        init_laws();
        invalidate_tlb(0);
-#ifdef CONFIG_FSL_INIT_TLBS
        init_tlbs();
-#else
-       {
-               extern u32 tlb1_entry;
-               u32 *tmp = &tlb1_entry;
-               int i;
-               int num = tmp[2];
-
-               /* skip to actual table */
-               tmp += 3;
-
-               for (i = 0; i < num; i++, tmp += 4) {
-                       mtspr(MAS0, tmp[0]);
-                       mtspr(MAS1, tmp[1]);
-                       mtspr(MAS2, tmp[2]);
-                       mtspr(MAS3, tmp[3]);
-                       asm volatile("isync;msync;tlbwe;isync");
-               }
-       }
-#endif
 }
 
 /*
@@ -187,12 +174,6 @@ void cpu_init_f (void)
        disable_tlb(14);
        disable_tlb(15);
 
-       /* Pointer is writable since we allocated a register for it */
-       gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
-
-       /* Clear initial global data */
-       memset ((void *) gd, 0, sizeof (gd_t));
-
 #ifdef CONFIG_CPM2
        config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR);
 #endif
@@ -273,16 +254,7 @@ void cpu_init_f (void)
 
 int cpu_init_r(void)
 {
-#ifdef CONFIG_CLEAR_LAW0
-#ifdef CONFIG_FSL_LAW
-       disable_law(0);
-#else
-       volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
-
-       /* clear alternate boot location LAW (used for sdram, or ddr bank) */
-       ecm->lawar0 = 0;
-#endif
-#endif
+       puts ("L2:    ");
 
 #if defined(CONFIG_L2_CACHE)
        volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
@@ -291,7 +263,7 @@ int cpu_init_r(void)
        uint l2srbar;
 
        svr = get_svr();
-       ver = SVR_VER(svr);
+       ver = SVR_SOC_VER(svr);
 
        asm("msync;isync");
        cache_ctl = l2cache->l2ctl;
@@ -300,17 +272,17 @@ int cpu_init_r(void)
        case 0x20000000:
                if (ver == SVR_8548 || ver == SVR_8548_E ||
                    ver == SVR_8544 || ver == SVR_8568_E) {
-                       printf ("L2 cache 512KB:");
+                       puts ("512 KB ");
                        /* set L2E=1, L2I=1, & L2SRAM=0 */
                        cache_ctl = 0xc0000000;
                } else {
-                       printf ("L2 cache 256KB:");
+                       puts("256 KB ");
                        /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
                        cache_ctl = 0xc8000000;
                }
                break;
        case 0x10000000:
-               printf ("L2 cache 256KB:");
+               puts("256 KB ");
                if (ver == SVR_8544 || ver == SVR_8544_E) {
                        cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
                }
@@ -318,18 +290,18 @@ int cpu_init_r(void)
        case 0x30000000:
        case 0x00000000:
        default:
-               printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
+               printf(" unknown size (0x%08x)\n", cache_ctl);
                return -1;
        }
 
        if (l2cache->l2ctl & 0x80000000) {
-               printf(" already enabled.");
+               puts("already enabled");
                l2srbar = l2cache->l2srbar0;
 #ifdef CFG_INIT_L2_ADDR
                if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) {
                        l2srbar = CFG_INIT_L2_ADDR;
                        l2cache->l2srbar0 = l2srbar;
-                       printf("  Moving to 0x%08x", CFG_INIT_L2_ADDR);
+                       printf("moving to 0x%08x", CFG_INIT_L2_ADDR);
                }
 #endif /* CFG_INIT_L2_ADDR */
                puts("\n");
@@ -337,10 +309,10 @@ int cpu_init_r(void)
                asm("msync;isync");
                l2cache->l2ctl = cache_ctl; /* invalidate & enable */
                asm("msync;isync");
-               printf(" enabled\n");
+               puts("enabled\n");
        }
 #else
-       printf("L2 cache: disabled\n");
+       puts("disabled\n");
 #endif
 #ifdef CONFIG_QE
        uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */
@@ -348,5 +320,8 @@ int cpu_init_r(void)
        qe_reset();
 #endif
 
+#if defined(CONFIG_MP)
+       setup_mp();
+#endif
        return 0;
 }