/*
- * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
+ * Copyright 2004,2007-2009 Freescale Semiconductor, Inc.
* (C) Copyright 2002, 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
*
* MA 02111-1307 USA
*/
+#include <config.h>
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <fsl_esdhc.h>
#include <asm/cache.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
-struct cpu_type cpu_type_list [] = {
- CPU_TYPE_ENTRY(8533, 8533),
- CPU_TYPE_ENTRY(8533, 8533_E),
- CPU_TYPE_ENTRY(8540, 8540),
- CPU_TYPE_ENTRY(8541, 8541),
- CPU_TYPE_ENTRY(8541, 8541_E),
- CPU_TYPE_ENTRY(8543, 8543),
- CPU_TYPE_ENTRY(8543, 8543_E),
- CPU_TYPE_ENTRY(8544, 8544),
- CPU_TYPE_ENTRY(8544, 8544_E),
- CPU_TYPE_ENTRY(8545, 8545),
- CPU_TYPE_ENTRY(8545, 8545_E),
- CPU_TYPE_ENTRY(8547, 8547_E),
- CPU_TYPE_ENTRY(8548, 8548),
- CPU_TYPE_ENTRY(8548, 8548_E),
- CPU_TYPE_ENTRY(8555, 8555),
- CPU_TYPE_ENTRY(8555, 8555_E),
- CPU_TYPE_ENTRY(8560, 8560),
- CPU_TYPE_ENTRY(8567, 8567),
- CPU_TYPE_ENTRY(8567, 8567_E),
- CPU_TYPE_ENTRY(8568, 8568),
- CPU_TYPE_ENTRY(8568, 8568_E),
- CPU_TYPE_ENTRY(8572, 8572),
- CPU_TYPE_ENTRY(8572, 8572_E),
-};
-
-struct cpu_type *identify_cpu(u32 ver)
-{
- int i;
- for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
- if (cpu_type_list[i].soc_ver == ver)
- return &cpu_type_list[i];
-
- return NULL;
-}
-
int checkcpu (void)
{
sys_info_t sysinfo;
- uint lcrr; /* local bus clock ratio register */
- uint clkdiv; /* clock divider portion of lcrr */
uint pvr, svr;
uint fam;
uint ver;
uint major, minor;
struct cpu_type *cpu;
+ char buf1[32], buf2[32];
#ifdef CONFIG_DDR_CLK_FREQ
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+ >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
#else
u32 ddr_ratio = 0;
#endif
+ int i;
svr = get_svr();
- ver = SVR_SOC_VER(svr);
major = SVR_MAJ(svr);
+#ifdef CONFIG_MPC8536
+ major &= 0x7; /* the msb of this nibble is a mfg code */
+#endif
minor = SVR_MIN(svr);
- puts("CPU: ");
-
- cpu = identify_cpu(ver);
- if (cpu) {
- puts(cpu->name);
-
- if (svr & 0x80000)
- puts("E");
+ if (cpu_numcores() > 1) {
+ volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+ printf("CPU%d: ", pic->whoami);
} else {
- puts("Unknown");
+ puts("CPU: ");
}
+ cpu = gd->cpu;
+
+ puts(cpu->name);
+ if (IS_E_PROCESSOR(svr))
+ puts("E");
+
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
pvr = get_pvr();
puts("Unknown");
break;
}
+
+ if (PVR_MEM(pvr) == 0x03)
+ puts("MC");
+
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
get_sys_info(&sysinfo);
- puts("Clock Configuration:\n");
- printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
- printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));
+ puts("Clock Configuration:");
+ for (i = 0; i < cpu_numcores(); i++) {
+ if (!(i & 3))
+ printf ("\n ");
+ printf("CPU%d:%-4s MHz, ",
+ i,strmhz(buf1, sysinfo.freqProcessor[i]));
+ }
+ printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
switch (ddr_ratio) {
case 0x0:
- printf(" DDR:%4lu MHz (%lu MT/s data rate), ",
- DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
+ printf(" DDR:%-4s MHz (%s MT/s data rate), ",
+ strmhz(buf1, sysinfo.freqDDRBus/2),
+ strmhz(buf2, sysinfo.freqDDRBus));
break;
case 0x7:
- printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ",
- DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000));
+ printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ",
+ strmhz(buf1, sysinfo.freqDDRBus/2),
+ strmhz(buf2, sysinfo.freqDDRBus));
break;
default:
- printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ",
- DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
+ printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ",
+ strmhz(buf1, sysinfo.freqDDRBus/2),
+ strmhz(buf2, sysinfo.freqDDRBus));
break;
}
-#if defined(CFG_LBC_LCRR)
- lcrr = CFG_LBC_LCRR;
-#else
- {
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ if (sysinfo.freqLocalBus > LCRR_CLKDIV)
+ printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
+ else
+ printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
+ sysinfo.freqLocalBus);
- lcrr = lbc->lcrr;
- }
-#endif
- clkdiv = lcrr & 0x0f;
- if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
-#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
- /*
- * Yes, the entire PQ38 family use the same
- * bit-representation for twice the clock divider values.
- */
- clkdiv *= 2;
+#ifdef CONFIG_CPM2
+ printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
#endif
- printf("LBC:%4lu MHz\n",
- DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv);
- } else {
- printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
- }
-#ifdef CONFIG_CPM2
- printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
+#ifdef CONFIG_QE
+ printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
#endif
puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
if (ver & 1){
/* e500 v2 core has reset control register */
volatile unsigned int * rstcr;
- rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
+ rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0);
*rstcr = 0x2; /* HRESET_REQ */
udelay(100);
}
}
#endif /* CONFIG_WATCHDOG */
-#if defined(CONFIG_DDR_ECC)
-void dma_init(void) {
- volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
-
- dma->satr0 = 0x02c40000;
- dma->datr0 = 0x02c40000;
- dma->sr0 = 0xfffffff; /* clear any errors */
- asm("sync; isync; msync");
- return;
-}
-
-uint dma_check(void) {
- volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
- volatile uint status = dma->sr0;
-
- /* While the channel is busy, spin */
- while((status & 4) == 4) {
- status = dma->sr0;
- }
-
- /* clear MR0[CS] channel start bit */
- dma->mr0 &= 0x00000001;
- asm("sync;isync;msync");
-
- if (status != 0) {
- printf ("DMA Error: status = %x\n", status);
- }
- return status;
-}
-
-int dma_xfer(void *dest, uint count, void *src) {
- volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
-
- dma->dar0 = (uint) dest;
- dma->sar0 = (uint) src;
- dma->bcr0 = count;
- dma->mr0 = 0xf000004;
- asm("sync;isync;msync");
- dma->mr0 = 0xf000005;
- asm("sync;isync;msync");
- return dma_check();
-}
-#endif
/*
- * Configures a UPM. Currently, the loop fields in MxMR (RLF, WLF and TLF)
- * are hardcoded as "1"."size" is the number or entries, not a sizeof.
+ * Configures a UPM. The function requires the respective MxMR to be set
+ * before calling this function. "size" is the number or entries, not a sizeof.
*/
void upmconfig (uint upm, uint * table, uint size)
{
int i, mdr, mad, old_mad = 0;
volatile u32 *mxmr;
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
- int loopval = 0x00004440;
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile u32 *brp,*orp;
volatile u8* dummy = NULL;
int upmmask;
i++, brp += 2, orp += 2) {
/* Look for a valid BR with selected UPM */
- if ((in_be32(brp) & (BR_V | upmmask)) == (BR_V | upmmask)) {
- dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT);
+ if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
+ dummy = (volatile u8*)(in_be32(brp) & BR_BA);
break;
}
}
for (i = 0; i < size; i++) {
/* 1 */
- out_be32(mxmr, loopval | 0x10000000 | i); /* OP_WRITE */
+ out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
/* 2 */
out_be32(&lbc->mdr, table[i]);
/* 3 */
*(volatile u8 *)dummy = 0;
/* 5 */
do {
- mad = in_be32(mxmr) & 0x3f;
+ mad = in_be32(mxmr) & MxMR_MAD_MSK;
} while (mad <= old_mad && !(!mad && i == (size-1)));
old_mad = mad;
}
- out_be32(mxmr, loopval); /* OP_NORMAL */
+ out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
+}
+
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_FSL_ESDHC
+ return fsl_esdhc_mmc_init(bis);
+#else
+ return 0;
+#endif
}
projects / platform / kernel / u-boot.git / blobdiff