Merge with git://www.denx.de/git/u-boot.git

[platform/kernel/u-boot.git] / cpu / mpc83xx / spd_sdram.c

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index d9b8753..54f0c83 100644 (file)
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -58,8 +58,8 @@ picos_to_clk(int picos)
        int clks;
 
        ddr_bus_clk = gd->ddr_clk >> 1;
-       clks = picos / ((1000000000 / ddr_bus_clk) * 1000);
-       if (picos % ((1000000000 / ddr_bus_clk) * 1000) != 0)
+       clks = picos / (1000000000 / (ddr_bus_clk / 1000));
+       if (picos % (1000000000 / (ddr_bus_clk / 1000)) != 0)
                clks++;
 
        return clks;
@@ -574,7 +574,10 @@ long int spd_sdram()
 
        /* Check DIMM data bus width */
        if (spd.dataw_lsb == 0x20) {
-               burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
+               if (spd.mem_type == SPD_MEMTYPE_DDR)
+                       burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
+               else
+                       burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
                printf("\n   DDR DIMM: data bus width is 32 bit");
        } else {
                burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
@@ -624,7 +627,7 @@ long int spd_sdram()
                         | (1 << (16 + 10))             /* DQS Differential disable */
                         | (add_lat << (16 + 3))        /* Additive Latency in EMRS1 */
                         | (mode_odt_enable << 16)      /* ODT Enable in EMRS1 */
-                        | ((twr_clk >> 1) << 9)        /* Write Recovery Autopre */
+                        | ((twr_clk - 1) << 9)         /* Write Recovery Autopre */
                         | (caslat << 4)                /* caslat */
                         | (burstlen << 0)              /* Burst length */
                        );
@@ -693,11 +696,6 @@ long int spd_sdram()
 
 #ifdef CFG_DDR_SDRAM_CLK_CNTL  /* Optional platform specific value */
        ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
-#else
-       /* SS_EN = 0, source synchronous disable
-        * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd
-        */
-       ddr->sdram_clk_cntl = 0x00000000;
 #endif
        debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
 
@@ -735,8 +733,12 @@ long int spd_sdram()
                sdram_cfg |= 0x10000000;
 
        /* The DIMM is 32bit width */
-       if (spd.dataw_lsb == 0x20)
-               sdram_cfg |= 0x000C0000;
+       if (spd.dataw_lsb == 0x20) {
+               if (spd.mem_type == SPD_MEMTYPE_DDR)
+                       sdram_cfg |= 0x000C0000;
+               if (spd.mem_type == SPD_MEMTYPE_DDR2)
+                       sdram_cfg |= 0x00080000;
+       }
 
        ddrc_ecc_enable = 0;