* Cleanup lowboot code for MPC5200

[platform/kernel/u-boot.git] / cpu / mpc5xxx / start.S

diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S
index 216c1c8..a001e1c 100644 (file)
--- a/cpu/mpc5xxx/start.S
+++ b/cpu/mpc5xxx/start.S
@@ -103,6 +103,41 @@ boot_cold:
 boot_warm:
        mfmsr   r5                      /* save msr contents            */
 
+#if defined(CFG_LOWBOOT)
+       lis     r4, CFG_DEFAULT_MBAR@h
+       lis     r3,     0x0000FF00@h
+       ori     r3, r3, 0x0000FF00@l
+       stw     r3, 0x4(r4)
+       lis     r3,     0x0000FFFF@h
+       ori     r3, r3, 0x0000FFFF@l
+       stw     r3, 0x8(r4)
+       lis     r3,     0x00047800@h
+       ori     r3, r3, 0x00047800@l
+       stw     r3, 0x300(r4)
+       lis     r3,     0x02010000@h
+       ori     r3, r3, 0x02010000@l
+       stw     r3, 0x54(r4)
+
+       lis     r3,     lowboot_reentry@h
+       ori     r3, r3, lowboot_reentry@l
+       mtlr    r3
+       blr                             /* jump to flash based address */
+
+lowboot_reentry:
+       lis     r3,     0x0000FF00@h
+       ori     r3, r3, 0x0000FF00@l
+       stw     r3, 0x4c(r4)
+       lis     r3,     0x0000FFFF@h
+       ori     r3, r3, 0x0000FFFF@l
+       stw     r3, 0x50(r4)
+       lis     r3,     0x00047800@h
+       ori     r3, r3, 0x00047800@l
+       stw     r3, 0x300(r4)
+       lis     r3,     0x02000001@h
+       ori     r3, r3, 0x02000001@l
+       stw     r3, 0x54(r4)
+#endif /* CFG_LOWBOOT */
+
 #if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT)
        lis     r3, CFG_MBAR@h
        ori     r3, r3, CFG_MBAR@l
@@ -382,6 +417,14 @@ init_5xxx_core:
        mtspr   DBAT2L, r0
        mtspr   DBAT3U, r0
        mtspr   DBAT3L, r0
+       mtspr   DBAT4U, r0
+       mtspr   DBAT4L, r0
+       mtspr   DBAT5U, r0
+       mtspr   DBAT5L, r0
+       mtspr   DBAT6U, r0
+       mtspr   DBAT6L, r0
+       mtspr   DBAT7U, r0
+       mtspr   DBAT7L, r0
        mtspr   IBAT0U, r0
        mtspr   IBAT0L, r0
        mtspr   IBAT1U, r0
@@ -390,6 +433,14 @@ init_5xxx_core:
        mtspr   IBAT2L, r0
        mtspr   IBAT3U, r0
        mtspr   IBAT3L, r0
+       mtspr   IBAT4U, r0
+       mtspr   IBAT4L, r0
+       mtspr   IBAT5U, r0
+       mtspr   IBAT5L, r0
+       mtspr   IBAT6U, r0
+       mtspr   IBAT6L, r0
+       mtspr   IBAT7U, r0
+       mtspr   IBAT7L, r0
        SYNC
 
        /* invalidate all tlb's                                         */