#include <common.h>
#include <mpc5xxx.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* Breath some life into the CPU...
*
*/
void cpu_init_f (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
unsigned long addecr = (1 << 25); /* Boot_CS */
#if defined(CFG_RAMBOOT) && defined(CONFIG_MGT5100)
addecr |= (1 << 22); /* SDRAM enable */
#endif
#if defined(CFG_CS7_START) && defined(CFG_CS7_SIZE)
- *(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS5_START);
+ *(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS7_START);
*(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CFG_CS7_START, CFG_CS7_SIZE);
addecr |= (1 << 27);
#endif
/* enable timebase */
*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 13);
+ /* Enable snooping for RAM */
+ *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
+ *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CFG_SDRAM_BASE | 0x1d;
+
+# if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/* Motorola reports IPB should better run at 133 MHz. */
*(vu_long *)MPC5XXX_ADDECR |= 1;
/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
addecr = *(vu_long *)MPC5XXX_CDM_CFG;
addecr &= ~0x103;
+# if defined(CFG_PCICLK_EQUALS_IPBCLK_DIV2)
+ /* pci_clk_sel = 0x01 -> IPB_CLK/2 */
+ addecr |= 0x01;
+# else
+ /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
addecr |= 0x02;
+# endif /* CFG_PCICLK_EQUALS_IPBCLK_DIV2 */
*(vu_long *)MPC5XXX_CDM_CFG = addecr;
-#endif
+# endif /* CFG_IPBCLK_EQUALS_XLBCLK */
+ /* Configure the XLB Arbiter */
+ *(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff;
+ *(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111;
+
+# if defined(CFG_XLB_PIPELINING)
+ /* Enable piplining */
+ *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
+# endif
+#endif /* CONFIG_MPC5200 */
}
/*
#endif
*(vu_long *)MPC5XXX_ICTL_CRIT |= 0x0001ffff;
*(vu_long *)MPC5XXX_ICTL_EXT &= ~0x00000f00;
+ /* route critical ints to normal ints */
+ *(vu_long *)MPC5XXX_ICTL_EXT |= 0x00000001;
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC5XXX_FEC)
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
/* load FEC microcode */
loadtask(0, 2);
#endif