Set SDelay register in the DDR controller for the MPC5200B chip.

[kernel/u-boot.git] / cpu / mpc5xxx / cpu.c

diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c
index c481d18..8d1e7c6 100644 (file)
--- a/cpu/mpc5xxx/cpu.c
+++ b/cpu/mpc5xxx/cpu.c
@@ -37,15 +37,31 @@ int checkcpu (void)
 
        ulong clock = gd->cpu_clk;
        char buf[32];
+#ifndef CONFIG_MGT5100
+       uint svr, pvr;
+#endif
 
        puts ("CPU:   ");
 
-       printf (CPU_ID_STR);
-
+#ifdef CONFIG_MGT5100
+       puts   (CPU_ID_STR);
        printf (" (JTAG ID %08lx)", *(vu_long *)MPC5XXX_CDM_JTAGID);
-
+#else
+       svr = get_svr();
+       pvr = get_pvr();
+       switch (SVR_VER (svr)) {
+       case SVR_MPC5200:
+               printf ("MPC5200");
+               break;
+       default:
+               printf ("MPC52??  (SVR %08x)", svr);
+               break;
+       }
+
+       printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr), 
+               PVR_MAJ(pvr), PVR_MIN(pvr));
+#endif
        printf (" at %s MHz\n", strmhz (buf, clock));
-
        return 0;
 }
 
@@ -62,8 +78,9 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
        __asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
 
        /* Charge the watchdog timer */
-       *(vu_long *)(MPC5XXX_GPT0_COUNTER) = 0xf;
+       *(vu_long *)(MPC5XXX_GPT0_COUNTER) = 0x0001000f;
        *(vu_long *)(MPC5XXX_GPT0_ENABLE) = 0x9004; /* wden|ce|timer_ms */
+       while(1);
 
        return 1;