[MIPS] cpu/mips/cache.S: Fix build warning

[platform/kernel/u-boot.git] / cpu / mips / cache.S

diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index bb42616..1b0efc3 100644 (file)
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -1,5 +1,5 @@
 /*
- *  Cache-handling routined for MIPS 4K CPUs
+ *  Cache-handling routined for MIPS CPUs
  *
  *  Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
  *
@@ -32,10 +32,14 @@
 
 #define RA             t8
 
-       /* 16KB is the maximum size of instruction and data caches on
-        * MIPS 4K.
-        */
-#define MIPS_MAX_CACHE_SIZE    0x4000
+/*
+ * 16kB is the maximum size of instruction and data caches on MIPS 4K,
+ * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
+ *
+ * Note that the above size is the maximum size of primary cache. U-Boot
+ * doesn't have L2 cache support for now.
+ */
+#define MIPS_MAX_CACHE_SIZE    0x10000
 
 #define INDEX_BASE     KSEG0
 
@@ -236,14 +240,16 @@ NESTED(mips_cache_reset, 0, ra)
         */
        move    a1, t2
        move    a2, t4
-       bal     mips_init_icache
+       PTR_LA  t7, mips_init_icache
+       jalr    t7
 
        /*
         * then initialize D-cache.
         */
        move    a1, t3
        move    a2, t5
-       bal     mips_init_dcache
+       PTR_LA  t7, mips_init_dcache
+       jalr    t7
 
        jr      RA
        END(mips_cache_reset)
@@ -256,9 +262,13 @@ NESTED(mips_cache_reset, 0, ra)
 *
 */
 LEAF(dcache_status)
-       mfc0    v0, CP0_CONFIG
-       andi    v0, v0, 1
-       j       ra
+       mfc0    t0, CP0_CONFIG
+       li      t1, CONF_CM_UNCACHED
+       andi    t0, t0, CONF_CM_CMASK
+       move    v0, zero
+       beq     t0, t1, 2f
+       li      v0, 1
+2:     jr      ra
        END(dcache_status)
 
 /*******************************************************************************
@@ -274,9 +284,25 @@ LEAF(dcache_disable)
        and     t0, t0, t1
        ori     t0, t0, CONF_CM_UNCACHED
        mtc0    t0, CP0_CONFIG
-       j       ra
+       jr      ra
        END(dcache_disable)
 
+/*******************************************************************************
+*
+* dcache_enable - enable cache
+*
+* RETURNS: N/A
+*
+*/
+LEAF(dcache_enable)
+       mfc0    t0, CP0_CONFIG
+       ori     t0, CONF_CM_CMASK
+       xori    t0, CONF_CM_CMASK
+       ori     t0, CONF_CM_CACHABLE_NONCOHERENT
+       mtc0    t0, CP0_CONFIG
+       jr      ra
+       END(dcache_enable)
+
 #ifdef CFG_INIT_RAM_LOCK_MIPS
 /*******************************************************************************
 *
@@ -300,7 +326,7 @@ mips_cache_lock:
        move    a1, a2
        icacheop(a0,a1,a2,a3,0x1d)
 
-       j       ra
+       jr      ra
 
        .end    mips_cache_lock
 #endif /* CFG_INIT_RAM_LOCK_MIPS */