dma_range[0] = 0;
if (size >= 0x100000000ull)
- dma_range[0] |= FDT_PCI_MEM64;
+ dma_range[0] |= cpu_to_fdt32(FDT_PCI_MEM64);
else
- dma_range[0] |= FDT_PCI_MEM32;
+ dma_range[0] |= cpu_to_fdt32(FDT_PCI_MEM32);
if (hose->regions[r].flags & PCI_REGION_PREFETCH)
- dma_range[0] |= FDT_PCI_PREFETCH;
+ dma_range[0] |= cpu_to_fdt32(FDT_PCI_PREFETCH);
#ifdef CONFIG_SYS_PCI_64BIT
- dma_range[1] = bus_start >> 32;
+ dma_range[1] = cpu_to_fdt32(bus_start >> 32);
#else
dma_range[1] = 0;
#endif
- dma_range[2] = bus_start & 0xffffffff;
+ dma_range[2] = cpu_to_fdt32(bus_start & 0xffffffff);
if (addrcell == 2) {
- dma_range[3] = phys_start >> 32;
- dma_range[4] = phys_start & 0xffffffff;
+ dma_range[3] = cpu_to_fdt32(phys_start >> 32);
+ dma_range[4] = cpu_to_fdt32(phys_start & 0xffffffff);
} else {
- dma_range[3] = phys_start & 0xffffffff;
+ dma_range[3] = cpu_to_fdt32(phys_start & 0xffffffff);
}
if (sizecell == 2) {
- dma_range[3 + addrcell + 0] = size >> 32;
- dma_range[3 + addrcell + 1] = size & 0xffffffff;
+ dma_range[3 + addrcell + 0] =
+ cpu_to_fdt32(size >> 32);
+ dma_range[3 + addrcell + 1] =
+ cpu_to_fdt32(size & 0xffffffff);
} else {
- dma_range[3 + addrcell + 0] = size & 0xffffffff;
+ dma_range[3 + addrcell + 0] =
+ cpu_to_fdt32(size & 0xffffffff);
}
dma_range += (3 + addrcell + sizecell);
return __of_translate_address(blob, node_offset, in_addr, "ranges");
}
+u64 fdt_translate_dma_address(const void *blob, int node_offset,
+ const fdt32_t *in_addr)
+{
+ return __of_translate_address(blob, node_offset, in_addr, "dma-ranges");
+}
+
/**
* fdt_node_offset_by_compat_reg: Find a node that matches compatiable and
* who's reg property matches a physical cpu address
prop = fdt_getprop(fdt, node, "reg", &size);
- return prop ? fdt_translate_address(fdt, node, prop) : 0;
+ return prop ? fdt_translate_address(fdt, node, prop) : OF_BAD_ADDR;
}
/*