#include <common.h>
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if defined(CONFIG_CMD_NAND)
#ifdef CONFIG_NEW_NAND_CODE
#include <nand.h>
/*
* not required for Monahans DFC
*/
-static void dfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
return;
}
}
-/*
- * These functions are quite problematic for the DFC. Luckily they are
- * not used in the current nand code, except for nand_command, which
- * we've defined our own anyway. The problem is, that we always need
- * to write 4 bytes to the DFC Data Buffer, but in these functions we
- * don't know if to buffer the bytes/half words until we've gathered 4
- * bytes or if to send them straight away.
- *
- * Solution: Don't use these with Mona's DFC and complain loudly.
- */
-static void dfc_write_word(struct mtd_info *mtd, u16 word)
-{
- printf("dfc_write_word: WARNING, this function does not work with the Monahans DFC!\n");
-}
-static void dfc_write_byte(struct mtd_info *mtd, u_char byte)
-{
- printf("dfc_write_byte: WARNING, this function does not work with the Monahans DFC!\n");
-}
-
/* The original:
* static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
*
*/
static u16 dfc_read_word(struct mtd_info *mtd)
{
- printf("dfc_write_byte: UNIMPLEMENTED.\n");
+ printf("dfc_read_word: UNIMPLEMENTED.\n");
return 0;
}
break;
}
if(get_delta(start) > timeout) {
- DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event);
+ DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
return 0xff000000;
}
/* this function is called after Programm and Erase Operations to
* check for success or failure */
-static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
+static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
{
unsigned long ndsr=0, event=0;
+ int state = this->state;
if(state == FL_WRITING) {
event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
* argument are board-specific (per include/linux/mtd/nand_new.h):
* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - cmd_ctrl: hardwarespecific function for accesing control-lines
* - dev_ready: hardwarespecific function for accesing device ready/busy line
* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
* only be provided if a hardware ECC is available
- * - eccmode: mode of ecc, see defines
+ * - ecc.mode: mode of ecc, see defines
* - chip_delay: chip dependent delay for transfering data from array to
* read regs (tR)
* - options: various chip options. They can partly be set to inform
/* wait 10 us due to cmd buffer clear reset */
/* wait(10); */
-
- nand->hwcontrol = dfc_hwcontrol;
+ nand->cmd_ctrl = dfc_hwcontrol;
/* nand->dev_ready = dfc_device_ready; */
- nand->eccmode = NAND_ECC_SOFT;
+ nand->ecc.mode = NAND_ECC_SOFT;
nand->options = NAND_BUSWIDTH_16;
nand->waitfunc = dfc_wait;
nand->read_byte = dfc_read_byte;
- nand->write_byte = dfc_write_byte;
nand->read_word = dfc_read_word;
- nand->write_word = dfc_write_word;
nand->read_buf = dfc_read_buf;
nand->write_buf = dfc_write_buf;
nand->cmdfunc = dfc_cmdfunc;
- nand->autooob = &delta_oob;
+/* nand->autooob = &delta_oob; */
nand->badblock_pattern = &delta_bbt_descr;
return 0;
}