ARM64: zynqmp: Add support for SD1 boot mode

[platform/kernel/u-boot.git] / board / xilinx / zynqmp / zynqmp.c

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 0c9a814..6bdec20 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -9,9 +9,12 @@
 #include <netdev.h>
 #include <ahci.h>
 #include <scsi.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -26,10 +29,18 @@ int board_early_init_r(void)
 {
        u32 val;
 
-       val = readl(&crlapb_base->timestamp_ref_ctrl);
-       val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
-       writel(val, &crlapb_base->timestamp_ref_ctrl);
-
+       if (current_el() == 3) {
+               val = readl(&crlapb_base->timestamp_ref_ctrl);
+               val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
+               writel(val, &crlapb_base->timestamp_ref_ctrl);
+
+               /* Program freq register in System counter */
+               writel(zynqmp_get_system_timer_freq(),
+                      &iou_scntr_secure->base_frequency_id_register);
+               /* And enable system counter */
+               writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
+                      &iou_scntr_secure->counter_control_register);
+       }
        /* Program freq register in System counter and enable system counter */
        writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
        writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
@@ -63,53 +74,6 @@ void scsi_init(void)
 }
 #endif
 
-int board_eth_init(bd_t *bis)
-{
-       u32 ret = 0;
-
-#if defined(CONFIG_ZYNQ_GEM)
-# if defined(CONFIG_ZYNQ_GEM0)
-       ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
-                                               CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
-# endif
-# if defined(CONFIG_ZYNQ_GEM1)
-       ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
-                                               CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
-# endif
-# if defined(CONFIG_ZYNQ_GEM2)
-       ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2,
-                                               CONFIG_ZYNQ_GEM_PHY_ADDR2, 0);
-# endif
-# if defined(CONFIG_ZYNQ_GEM3)
-       ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3,
-                                               CONFIG_ZYNQ_GEM_PHY_ADDR3, 0);
-# endif
-#endif
-       return ret;
-}
-
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bd)
-{
-       int ret = 0;
-
-       u32 ver = zynqmp_get_silicon_version();
-
-       if (ver != ZYNQMP_CSU_VERSION_VELOCE) {
-#if defined(CONFIG_ZYNQ_SDHCI)
-# if defined(CONFIG_ZYNQ_SDHCI0)
-               ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
-# endif
-# if defined(CONFIG_ZYNQ_SDHCI1)
-               ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
-# endif
-#endif
-       }
-
-       return ret;
-}
-#endif
-
 int board_late_init(void)
 {
        u32 reg = 0;
@@ -119,10 +83,23 @@ int board_late_init(void)
        bootmode = reg & BOOT_MODES_MASK;
 
        switch (bootmode) {
+       case JTAG_MODE:
+               setenv("modeboot", "netboot");
+               break;
+       case QSPI_MODE_24BIT:
+       case QSPI_MODE_32BIT:
+               setenv("modeboot", "qspiboot");
+               break;
        case SD_MODE:
        case EMMC_MODE:
                setenv("modeboot", "sdboot");
                break;
+       case SD_MODE1:
+               setenv("modeboot", "sdboot1");
+               break;
+       case NAND_MODE:
+               setenv("modeboot", "nandboot");
+               break;
        default:
                printf("Invalid Boot Mode:0x%x\n", bootmode);
                break;
@@ -130,3 +107,35 @@ int board_late_init(void)
 
        return 0;
 }
+
+int checkboard(void)
+{
+       puts("Board:\tXilinx ZynqMP\n");
+       return 0;
+}
+
+#ifdef CONFIG_USB_DWC3
+static struct dwc3_device dwc3_device_data = {
+       .maximum_speed = USB_SPEED_HIGH,
+       .base = ZYNQMP_USB0_XHCI_BASEADDR,
+       .dr_mode = USB_DR_MODE_PERIPHERAL,
+       .index = 0,
+};
+
+int usb_gadget_handle_interrupts(void)
+{
+       dwc3_uboot_handle_interrupt(0);
+       return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+       return dwc3_uboot_init(&dwc3_device_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+       dwc3_uboot_exit(index);
+       return 0;
+}
+#endif