#include <fdtdec.h>
#include <fpga.h>
#include <mmc.h>
-#include <netdev.h>
#include <zynqpl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
static xilinx_desc fpga;
/* It can be done differently */
+static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
+static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
idcode = zynq_slcr_get_idcode();
switch (idcode) {
+ case XILINX_ZYNQ_7007S:
+ fpga = fpga007s;
+ break;
case XILINX_ZYNQ_7010:
fpga = fpga010;
break;
+ case XILINX_ZYNQ_7012S:
+ fpga = fpga012s;
+ break;
+ case XILINX_ZYNQ_7014S:
+ fpga = fpga014s;
+ break;
case XILINX_ZYNQ_7015:
fpga = fpga015;
break;
int board_late_init(void)
{
switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+ case ZYNQ_BM_QSPI:
+ setenv("modeboot", "qspiboot");
+ break;
+ case ZYNQ_BM_NAND:
+ setenv("modeboot", "nandboot");
+ break;
case ZYNQ_BM_NOR:
setenv("modeboot", "norboot");
break;
return 0;
}
-int board_eth_init(bd_t *bis)
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
{
- u32 ret = 0;
-
-#ifdef CONFIG_XILINX_AXIEMAC
- ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
- XILINX_AXIDMA_BASEADDR);
-#endif
-#ifdef CONFIG_XILINX_EMACLITE
- u32 txpp = 0;
- u32 rxpp = 0;
-# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
- txpp = 1;
-# endif
-# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
- rxpp = 1;
-# endif
- ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
- txpp, rxpp);
+ puts("Board: Xilinx Zynq\n");
+ return 0;
+}
#endif
-#if defined(CONFIG_ZYNQ_GEM)
-# if defined(CONFIG_ZYNQ_GEM0)
- ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
- CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
-# endif
-# if defined(CONFIG_ZYNQ_GEM1)
- ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
- CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
-# endif
+int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
+{
+#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
+ defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
+ if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
+ CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
+ ethaddr, 6))
+ printf("I2C EEPROM MAC address read failed\n");
#endif
- return ret;
+
+ return 0;
}
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bd)
+#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+int dram_init_banksize(void)
{
- int ret = 0;
-
-#if defined(CONFIG_ZYNQ_SDHCI)
-# if defined(CONFIG_ZYNQ_SDHCI0)
- ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
-# endif
-# if defined(CONFIG_ZYNQ_SDHCI1)
- ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
-# endif
-#endif
- return ret;
+ fdtdec_setup_memory_banksize();
+
+ return 0;
}
-#endif
int dram_init(void)
{
-#ifdef CONFIG_OF_CONTROL
- int node;
- fdt_addr_t addr;
- fdt_size_t size;
- const void *blob = gd->fdt_blob;
-
- node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
- "memory", 7);
- if (node == -FDT_ERR_NOTFOUND) {
- debug("ZYNQ DRAM: Can't get memory node\n");
- return -1;
- }
- addr = fdtdec_get_addr_size(blob, node, "reg", &size);
- if (addr == FDT_ADDR_T_NONE || size == 0) {
- debug("ZYNQ DRAM: Can't get base address or size\n");
- return -1;
- }
- gd->ram_size = size;
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
+
+ zynq_ddrc_init();
+
+ return 0;
+}
#else
+int dram_init(void)
+{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-#endif
+
zynq_ddrc_init();
return 0;
}
+#endif