Merge tag 'xilinx-for-v2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot...

[platform/kernel/u-boot.git] / board / xilinx / zynq / board.c

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 2f17e97..7cfe69d 100644 (file)
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -1,123 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
- *
- * SPDX-License-Identifier:    GPL-2.0+
+ * (C) Copyright 2013 - 2018 Xilinx, Inc.
  */
 
 #include <common.h>
+#include <dm/uclass.h>
+#include <env.h>
 #include <fdtdec.h>
 #include <fpga.h>
+#include <malloc.h>
 #include <mmc.h>
+#include <watchdog.h>
+#include <wdt.h>
 #include <zynqpl.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
-    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
-static xilinx_desc fpga;
-
-/* It can be done differently */
-static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
-static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
-static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
-static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
-static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
-static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
-static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+       return 0;
+}
 #endif
 
 int board_init(void)
 {
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
-    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
-       u32 idcode;
-
-       idcode = zynq_slcr_get_idcode();
-
-       switch (idcode) {
-       case XILINX_ZYNQ_7010:
-               fpga = fpga010;
-               break;
-       case XILINX_ZYNQ_7015:
-               fpga = fpga015;
-               break;
-       case XILINX_ZYNQ_7020:
-               fpga = fpga020;
-               break;
-       case XILINX_ZYNQ_7030:
-               fpga = fpga030;
-               break;
-       case XILINX_ZYNQ_7035:
-               fpga = fpga035;
-               break;
-       case XILINX_ZYNQ_7045:
-               fpga = fpga045;
-               break;
-       case XILINX_ZYNQ_7100:
-               fpga = fpga100;
-               break;
-       }
-#endif
-
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
-    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
-       fpga_init();
-       fpga_add(fpga_xilinx, &fpga);
-#endif
-
        return 0;
 }
 
 int board_late_init(void)
 {
+       int env_targets_len = 0;
+       const char *mode;
+       char *new_targets;
+       char *env_targets;
+
        switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+       case ZYNQ_BM_QSPI:
+               mode = "qspi";
+               env_set("modeboot", "qspiboot");
+               break;
+       case ZYNQ_BM_NAND:
+               mode = "nand";
+               env_set("modeboot", "nandboot");
+               break;
        case ZYNQ_BM_NOR:
-               setenv("modeboot", "norboot");
+               mode = "nor";
+               env_set("modeboot", "norboot");
                break;
        case ZYNQ_BM_SD:
-               setenv("modeboot", "sdboot");
+               mode = "mmc0";
+               env_set("modeboot", "sdboot");
                break;
        case ZYNQ_BM_JTAG:
-               setenv("modeboot", "jtagboot");
+               mode = "pxe dhcp";
+               env_set("modeboot", "jtagboot");
                break;
        default:
-               setenv("modeboot", "");
+               mode = "";
+               env_set("modeboot", "");
                break;
        }
 
+       /*
+        * One terminating char + one byte for space between mode
+        * and default boot_targets
+        */
+       env_targets = env_get("boot_targets");
+       if (env_targets)
+               env_targets_len = strlen(env_targets);
+
+       new_targets = calloc(1, strlen(mode) + env_targets_len + 2);
+       if (!new_targets)
+               return -ENOMEM;
+
+       sprintf(new_targets, "%s %s", mode,
+               env_targets ? env_targets : "");
+
+       env_set("boot_targets", new_targets);
+
        return 0;
 }
 
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
+#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+int dram_init_banksize(void)
 {
-       puts("Board: Xilinx Zynq\n");
-       return 0;
+       return fdtdec_setup_memory_banksize();
 }
-#endif
 
 int dram_init(void)
 {
-       int node;
-       fdt_addr_t addr;
-       fdt_size_t size;
-       const void *blob = gd->fdt_blob;
-
-       node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
-                                            "memory", 7);
-       if (node == -FDT_ERR_NOTFOUND) {
-               debug("ZYNQ DRAM: Can't get memory node\n");
-               return -1;
-       }
-       addr = fdtdec_get_addr_size(blob, node, "reg", &size);
-       if (addr == FDT_ADDR_T_NONE || size == 0) {
-               debug("ZYNQ DRAM: Can't get base address or size\n");
-               return -1;
-       }
-       gd->ram_size = size;
+       if (fdtdec_setup_mem_size_base() != 0)
+               return -EINVAL;
+
        zynq_ddrc_init();
 
        return 0;
 }
+#else
+int dram_init(void)
+{
+       gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+                                   CONFIG_SYS_SDRAM_SIZE);
+
+       zynq_ddrc_init();
+
+       return 0;
+}
+#endif