ppc: Remove kmcoge4 board

[platform/kernel/u-boot.git] / board / xes / xpedite550x / ddr.c

diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c
index 718cd98..ad52c94 100644 (file)
--- a/board/xes/xpedite550x/ddr.c
+++ b/board/xes/xpedite550x/ddr.c
@@ -1,70 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2010 Extreme Engineering Solutions, Inc.
  * Copyright 2007-2008 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
  */
 
 #include <common.h>
 #include <i2c.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
-static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
+void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address)
 {
        i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
                 sizeof(ddr3_spd_eeprom_t));
 }
 
-void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
-                     unsigned int ctrl_num)
-{
-       unsigned int i;
-       unsigned int i2c_address = 0;
-
-       for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
-               if (ctrl_num == 0 && i == 0)
-                       i2c_address = SPD_EEPROM_ADDRESS1;
-               get_spd(&(ctrl_dimms_spd[i]), i2c_address);
-       }
-}
-
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
 /*
  *     There are traditionally three board-specific SDRAM timing parameters
  *     which must be calculated based on the particular PCB artwork.  These are:
  *     1.) CPO (Read Capture Delay)
- *             - TIMING_CFG_2 register
- *             Source: Calculation based on board trace lengths and
- *                     chip-specific internal delays.
+ *            - TIMING_CFG_2 register
+ *            Source: Calculation based on board trace lengths and
+ *                    chip-specific internal delays.
  *     2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
- *             - DDR_SDRAM_CLK_CNTL register
- *             Source: Signal Integrity Simulations
+ *            - DDR_SDRAM_CLK_CNTL register
+ *            Source: Signal Integrity Simulations
  *     3.) 2T Timing on Addr/Ctl
- *             - TIMING_CFG_2 register
- *             Source: Signal Integrity Simulations
- *             Usually only needed with heavy load/very high speed (>DDR2-800)
+ *            - TIMING_CFG_2 register
+ *            Source: Signal Integrity Simulations
+ *            Usually only needed with heavy load/very high speed (>DDR2-800)
  *
  *     ====== XPedite550x DDR3-800 read delay calculations ======
  *
@@ -82,14 +47,14 @@ typedef struct {
 const board_specific_parameters_t board_specific_parameters[][20] = {
        {
                /* Controller 0 */
-                {
+               {
                        /* DDR3-600/667 */
                        .datarate_mhz_low       = 500,
                        .datarate_mhz_high      = 750,
                        .clk_adjust             = 5,
                        .cpo                    = 31,
                },
-                {
+               {
                        /* DDR3-800 */
                        .datarate_mhz_low       = 750,
                        .datarate_mhz_high      = 850,
@@ -142,11 +107,17 @@ void fsl_ddr_board_options(memctl_options_t *popts,
                    ddr_freq <= pbsp->datarate_mhz_high) {
                        popts->clk_adjust = pbsp->clk_adjust;
                        popts->cpo_override = pbsp->cpo;
-                       popts->twoT_en = 0;
+                       popts->twot_en = 0;
+                       break;
                }
                pbsp++;
        }
 
+       if (i == num_params) {
+               printf("Warning: board specific timing not found "
+               "for data rate %lu MT/s!\n", ddr_freq);
+       }
+
        /*
         * Factors to consider for half-strength driver enable:
         *      - number of DIMMs installed
@@ -162,4 +133,3 @@ void fsl_ddr_board_options(memctl_options_t *popts,
        popts->rtt_override = 1;
        popts->rtt_override_value = 3;
 }
-