global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

[platform/kernel/u-boot.git] / board / wandboard / spl.c

diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c
index d03ab43..717e02a 100644 (file)
--- a/board/wandboard/spl.c
+++ b/board/wandboard/spl.c
@@ -1,26 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2014 Wandboard
  * Author: Tungyi Lin <tungyilin1127@gmail.com>
  *         Richard Hu <hakahu@gmail.com>
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
+#include <common.h>
+#include <init.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
+#include <linux/delay.h>
 #include <linux/errno.h>
 #include <asm/gpio.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/video.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <spl.h>
 
-#if defined(CONFIG_SPL_BUILD)
 #include <asm/arch/mx6-ddr.h>
 /*
  * Driving strength:
@@ -422,4 +424,94 @@ void board_init_f(ulong dummy)
        /* DDR initialization */
        spl_dram_init();
 }
-#endif
+
+#define USDHC1_CD_GPIO         IMX_GPIO_NR(1, 2)
+#define USDHC3_CD_GPIO         IMX_GPIO_NR(3, 9)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                   \
+       PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+       {USDHC3_BASE_ADDR},
+       {USDHC1_BASE_ADDR},
+};
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+       IOMUX_PADS(PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       /* Carrier MicroSD Card Detect */
+       IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+       IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       /* SOM MicroSD Card Detect */
+       IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+       int ret = 0;
+
+       switch (cfg->esdhc_base) {
+       case USDHC1_BASE_ADDR:
+               ret = !gpio_get_value(USDHC1_CD_GPIO);
+               break;
+       case USDHC3_BASE_ADDR:
+               ret = !gpio_get_value(USDHC3_CD_GPIO);
+               break;
+       }
+
+       return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+       int ret;
+       u32 index = 0;
+
+       /*
+        * Following map is done:
+        * (U-Boot device node)    (Physical Port)
+        * mmc0                    SOM MicroSD
+        * mmc1                    Carrier board MicroSD
+        */
+       for (index = 0; index < CFG_SYS_FSL_USDHC_NUM; ++index) {
+               switch (index) {
+               case 0:
+                       SETUP_IOMUX_PADS(usdhc3_pads);
+                       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+                       usdhc_cfg[0].max_bus_width = 4;
+                       gpio_direction_input(USDHC3_CD_GPIO);
+                       break;
+               case 1:
+                       SETUP_IOMUX_PADS(usdhc1_pads);
+                       usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+                       usdhc_cfg[1].max_bus_width = 4;
+                       gpio_direction_input(USDHC1_CD_GPIO);
+                       break;
+               default:
+                       printf("Warning: you configured more USDHC controllers"
+                              "(%d) then supported by the board (%d)\n",
+                              index + 1, CFG_SYS_FSL_USDHC_NUM);
+                       return -EINVAL;
+               }
+
+               ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}