/*
* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
- * PPCboot port on RPXlite board
+ * U-Boot port on RPXlite board
*
* DRAM related UPMA register values are modified.
* See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
/* ------------------------------------------------------------------------- */
-#define MBYTE (1024*1024)
-#define DRAM_DELAY 0x00000379 /* DRAM delay count */
+#define MBYTE (1024*1024)
+#define DRAM_DELAY 0x00000379 /* DRAM delay count */
#define _NOT_USED_ 0xFFFFCC25
const uint sdram_table[] =
{
- /* single read. (offset 0 in upm RAM) */
- 0x1F07D004, 0xEEAEE004, 0x11ADD004, 0xEFBBA000,
- 0x1FF75447, 0x1FF77C34, 0xEFEABC34, 0x1FB57C35,
-
- /* burst read. (Offset 8 in upm RAM) */
- 0x1F07D004, 0xEEAEE004, 0x00ADC004, 0x00AFC000,
- 0x00AFC000, 0x01AFC000, 0x0FBB8000, 0x1FF75447,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* single write. (Offset 0x18 in upm RAM) */
- 0x1F27D004, 0xEEAEA000, 0x01B90004, 0x1FF75447,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* burst write. (Offset 0x20 in upm RAM) */
- 0x1F07D004, 0xEEAEA000, 0x00AD4000, 0x00AFC000,
- 0x00AFC000, 0x01BB8004, 0x1FF75447, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Refresh cycle, offset 0x30 */
- 0x1FF5DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC84, 0xFFFFFC07, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Exception, 0ffset 0x3C */
- 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ /* single read. (offset 0 in upm RAM) */
+ 0x1F07D004, 0xEEAEE004, 0x11ADD004, 0xEFBBA000,
+ 0x1FF75447, 0x1FF77C34, 0xEFEABC34, 0x1FB57C35,
+
+ /* burst read. (Offset 8 in upm RAM) */
+ 0x1F07D004, 0xEEAEE004, 0x00ADC004, 0x00AFC000,
+ 0x00AFC000, 0x01AFC000, 0x0FBB8000, 0x1FF75447,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* single write. (Offset 0x18 in upm RAM) */
+ 0x1F27D004, 0xEEAEA000, 0x01B90004, 0x1FF75447,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* burst write. (Offset 0x20 in upm RAM) */
+ 0x1F07D004, 0xEEAEA000, 0x00AD4000, 0x00AFC000,
+ 0x00AFC000, 0x01BB8004, 0x1FF75447, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* Refresh cycle, offset 0x30 */
+ 0x1FF5DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+ 0xFFFFFC84, 0xFFFFFC07, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* Exception, 0ffset 0x3C */
+ 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
};
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
delay_cnt = 0;
while( delay_cnt++ < DRAM_DELAY )
- ;
+ ;
/* Run MRS command in location 5-8 of UPMB */
delay_cnt = 0;
while( delay_cnt++ < DRAM_DELAY )
- ;
+ ;
#ifdef CONFIG_CAN_DRIVER
/* Initialize OR3 / BR3 */
memctl->memc_br3 = CFG_BR3_CAN;
/* Initialize MBMR */
- memctl->memc_mamr = MAMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
+ memctl->memc_mamr = MAMR_GPL_A4DIS; /* GPL_A4 ouput line Disable */
/* Initialize UPMB for CAN: single read */
memctl->memc_mdr = 0xFFFFC004;
switch( memory )
{
- case 1:
- return( 32*MBYTE );
- case 2:
- return( 64*MBYTE );
- default:
- break;
+ case 1:
+ return( 32*MBYTE );
+ case 2:
+ return( 64*MBYTE );
+ default:
+ break;
}
return( 16*MBYTE );
}