/* ------------------------------------------------------------------------- */
-#define MBYTE (1024*1024)
-#define DRAM_DELAY 0x00000379 /* DRAM delay count */
+#define MBYTE (1024*1024)
+#define DRAM_DELAY 0x00000379 /* DRAM delay count */
#define _NOT_USED_ 0xFFFFCC25
const uint sdram_table[] =
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
memctl->memc_br3 = CFG_BR3_CAN;
/* Initialize MBMR */
- memctl->memc_mamr = MAMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
+ memctl->memc_mamr = MAMR_GPL_A4DIS; /* GPL_A4 ouput line Disable */
/* Initialize UPMB for CAN: single read */
memctl->memc_mdr = 0xFFFFC004;