*/
#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx8-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <environment.h>
+#include <env.h>
#include <errno.h>
#include <linux/libfdt.h>
imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
}
+void board_mem_get_layout(u64 *phys_sdram_1_start,
+ u64 *phys_sdram_1_size,
+ u64 *phys_sdram_2_start,
+ u64 *phys_sdram_2_size)
+{
+ u32 is_dualx = 0, val = 0;
+ sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
+
+ if (scierr == SC_ERR_NONE) {
+ /* DX has two A35 cores disabled */
+ is_dualx = (val & 0xf) != 0x0;
+ }
+
+ *phys_sdram_1_start = PHYS_SDRAM_1;
+ if (is_dualx)
+ /* Our DX based SKUs only have 1 GB RAM */
+ *phys_sdram_1_size = SZ_1G;
+ else
+ *phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
+ *phys_sdram_2_start = PHYS_SDRAM_2;
+ *phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
+}
+
int board_early_init_f(void)
{
sc_pm_clock_rate_t rate;
return 0;
}
-void detail_board_ddr_info(void)
-{
- puts("\nDDR ");
-}
-
/*
* Board specific reset that is system reset.
*/
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, struct bd_info *bd)
{
return ft_common_board_setup(blob, bd);
}