board: ti: K2G FC SoC 1GHz and DDR3 1066 MT/s support

[platform/kernel/u-boot.git] / board / ti / ks2_evm / board_k2g.c

diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index 01328f1..88df419 100644 (file)
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -55,7 +55,7 @@ unsigned int get_external_clk(u32 clk)
        return clk_freq;
 }
 
-static int arm_speeds[DEVSPEED_NUMSPDS] = {
+int speeds[DEVSPEED_NUMSPDS] = {
        SPD400,
        SPD600,
        SPD800,
@@ -159,13 +159,20 @@ static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
        [SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
 };
 
-static struct pll_init_data ddr3_pll_config[MAX_SYSCLK] = {
+static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = {
        [SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
        [SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
        [SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
        [SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
 };
 
+static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = {
+       [SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
+       [SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
+       [SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
+       [SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
+};
+
 struct pll_init_data *get_pll_init_data(int pll)
 {
        int speed;
@@ -178,7 +185,7 @@ struct pll_init_data *get_pll_init_data(int pll)
                data = &main_pll_config[sysclk_index][speed];
                break;
        case TETRIS_PLL:
-               speed = get_max_arm_speed(arm_speeds);
+               speed = get_max_arm_speed(speeds);
                data = &tetris_pll_config[sysclk_index][speed];
                break;
        case NSS_PLL:
@@ -188,7 +195,15 @@ struct pll_init_data *get_pll_init_data(int pll)
                data = &uart_pll_config[sysclk_index];
                break;
        case DDR3_PLL:
-               data = &ddr3_pll_config[sysclk_index];
+               if (cpu_revision() & CPU_66AK2G1x) {
+                       speed = get_max_arm_speed(speeds);
+                       if (speed == SPD1000)
+                               data = &ddr3_pll_config_1066[sysclk_index];
+                       else
+                               data = &ddr3_pll_config_800[sysclk_index];
+               } else {
+                       data = &ddr3_pll_config_800[sysclk_index];
+               }
                break;
        default:
                data = NULL;
@@ -209,7 +224,7 @@ int board_mmc_init(bd_t *bis)
                return -1;
        }
 
-       if (board_is_k2g_gp())
+       if (board_is_k2g_gp() || board_is_k2g_g1())
                omap_mmc_init(0, 0, 0, -1, -1);
 
        omap_mmc_init(1, 0, 0, -1, -1);
@@ -224,7 +239,8 @@ int board_fit_config_name_match(const char *name)
 
        if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
                return 0;
-       else if (!strcmp(name, "keystone-k2g-evm") && board_ti_is("66AK2GGP"))
+       else if (!strcmp(name, "keystone-k2g-evm") &&
+               (board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
                return 0;
        else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
                return 0;
@@ -283,7 +299,7 @@ int embedded_dtb_select(void)
 
        k2g_reset_mux_config();
 
-       if (board_is_k2g_gp()) {
+       if (board_is_k2g_gp() || board_is_k2g_g1()) {
                /* deassert FLASH_HOLD */
                clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
                             BIT(9));
@@ -312,6 +328,8 @@ int board_late_init(void)
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
        if (board_is_k2g_gp())
                env_set("board_name", "66AK2GGP\0");
+       else if (board_is_k2g_g1())
+               env_set("board_name", "66AK2GG1\0");
        else if (board_is_k2g_ice())
                env_set("board_name", "66AK2GIC\0");
 #endif