{-1},
};
-static struct module_pin_mux gpio0_22_pin_mux[] = {
- {OFFSET(ddr_ba2), (MODE(9) | PULLUP_EN)}, /* GPIO0_22 */
+static struct module_pin_mux gpio5_7_pin_mux[] = {
+ {OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)}, /* GPIO5_7 */
+ {-1},
+};
+
+static struct module_pin_mux qspi_pin_mux[] = {
+ {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
+ {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
+ {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */
+ {OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */
+ {OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */
+ {OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */
{-1},
};
configure_module_pin_mux(i2c0_pin_mux);
if (board_is_gpevm())
- configure_module_pin_mux(gpio0_22_pin_mux);
+ configure_module_pin_mux(gpio5_7_pin_mux);
+ configure_module_pin_mux(qspi_pin_mux);
}
void enable_i2c0_pin_mux(void)