/* MII mode defines */
#define MII_MODE_ENABLE 0x0
-#define RGMII_MODE_ENABLE 0xA
+#define RGMII_MODE_ENABLE 0x3A
/* GPIO that controls power to DDR on EVM-SK */
#define GPIO_DDR_VTT_EN 7
return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
}
+static inline int board_is_idk(void)
+{
+ return !strncmp(header.config, "SKU#02", 6);
+}
+
/*
* Read header information from EEPROM into global structure.
*/
/* Enable the RTC 32K OSC by setting bits 3 and 6. */
writel((1 << 3) | (1 << 6), &rtc->osc);
}
-#endif
-/*
- * Determine what type of DDR we have.
- */
-static short inline board_memory_type(void)
-{
- /* The following boards are known to use DDR3. */
- if (board_is_evm_sk() || board_is_bone_lt())
- return EMIF_REG_SDRAM_TYPE_DDR3;
+static const struct ddr_data ddr2_data = {
+ .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
+ (MT47H128M16RT25E_RD_DQS<<20) |
+ (MT47H128M16RT25E_RD_DQS<<10) |
+ (MT47H128M16RT25E_RD_DQS<<0)),
+ .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
+ (MT47H128M16RT25E_WR_DQS<<20) |
+ (MT47H128M16RT25E_WR_DQS<<10) |
+ (MT47H128M16RT25E_WR_DQS<<0)),
+ .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
+ (MT47H128M16RT25E_PHY_WRLVL<<20) |
+ (MT47H128M16RT25E_PHY_WRLVL<<10) |
+ (MT47H128M16RT25E_PHY_WRLVL<<0)),
+ .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
+ (MT47H128M16RT25E_PHY_GATELVL<<20) |
+ (MT47H128M16RT25E_PHY_GATELVL<<10) |
+ (MT47H128M16RT25E_PHY_GATELVL<<0)),
+ .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
+ (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
+ (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
+ (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
+ .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
+ (MT47H128M16RT25E_PHY_WR_DATA<<20) |
+ (MT47H128M16RT25E_PHY_WR_DATA<<10) |
+ (MT47H128M16RT25E_PHY_WR_DATA<<0)),
+ .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
+ .datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
- return EMIF_REG_SDRAM_TYPE_DDR2;
-}
+static const struct cmd_control ddr2_cmd_ctrl_data = {
+ .cmd0csratio = MT47H128M16RT25E_RATIO,
+ .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
+ .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT47H128M16RT25E_RATIO,
+ .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
+ .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT47H128M16RT25E_RATIO,
+ .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
+ .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
+};
+
+static const struct emif_regs ddr2_emif_reg_data = {
+ .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
+ .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
+ .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
+ .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
+ .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
+ .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
+};
+
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41J128MJT125_RD_DQS,
+ .datawdsratio0 = MT41J128MJT125_WR_DQS,
+ .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
+ .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
+ .datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41J128MJT125_RATIO,
+ .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
+ .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41J128MJT125_RATIO,
+ .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
+ .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41J128MJT125_RATIO,
+ .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
+ .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = MT41J128MJT125_EMIF_SDCFG,
+ .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
+ .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
+ .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
+ .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
+ .zq_config = MT41J128MJT125_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
+};
+#endif
/*
* early system init of muxing and clocks.
/* UART softreset */
u32 regVal;
+#ifdef CONFIG_SERIAL1
enable_uart0_pin_mux();
+#endif /* CONFIG_SERIAL1 */
+#ifdef CONFIG_SERIAL2
+ enable_uart1_pin_mux();
+#endif /* CONFIG_SERIAL2 */
+#ifdef CONFIG_SERIAL3
+ enable_uart2_pin_mux();
+#endif /* CONFIG_SERIAL3 */
+#ifdef CONFIG_SERIAL4
+ enable_uart3_pin_mux();
+#endif /* CONFIG_SERIAL4 */
+#ifdef CONFIG_SERIAL5
+ enable_uart4_pin_mux();
+#endif /* CONFIG_SERIAL5 */
+#ifdef CONFIG_SERIAL6
+ enable_uart5_pin_mux();
+#endif /* CONFIG_SERIAL6 */
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_RESET;
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
- config_ddr(board_memory_type());
+ if (board_is_evm_sk() || board_is_bone_lt())
+ config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
+ else
+ config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
+ &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
#endif
}
gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+ gpmc_init();
+
return 0;
}
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ char safe_string[HDR_NAME_LEN + 1];
+
+ /* Now set variables based on the header. */
+ strncpy(safe_string, (char *)header.name, sizeof(header.name));
+ safe_string[sizeof(header.name)] = 0;
+ setenv("board_name", safe_string);
+
+ strncpy(safe_string, (char *)header.version, sizeof(header.version));
+ safe_string[sizeof(header.version)] = 0;
+ setenv("board_rev", safe_string);
+#endif
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_DRIVER_TI_CPSW
static void cpsw_control(int enabled)
{
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
+#endif
+#if defined(CONFIG_DRIVER_TI_CPSW) || \
+ (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
int board_eth_init(bd_t *bis)
{
+ int rv, n = 0;
+#ifdef CONFIG_DRIVER_TI_CPSW
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
if (is_valid_ether_addr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
else
- return -1;
+ goto try_usbether;
}
- if (board_is_bone() || board_is_bone_lt()) {
+ if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII;
PHY_INTERFACE_MODE_RGMII;
}
- return cpsw_register(&cpsw_data);
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+#endif
+try_usbether:
+#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
+ rv = usb_eth_initialize(bis);
+ if (rv < 0)
+ printf("Error %d registering USB_ETHER\n", rv);
+ else
+ n += rv;
+#endif
+ return n;
}
#endif