#include <common.h>
#include <mmc.h>
-#ifdef CONFIG_AXP152_POWER
-#include <axp152.h>
-#endif
-#ifdef CONFIG_AXP209_POWER
-#include <axp209.h>
-#endif
-#ifdef CONFIG_AXP221_POWER
-#include <axp221.h>
-#endif
+#include <axp_pmic.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include <asm/arch/display.h>
return 0;
}
-#if defined(CONFIG_SPL_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
static void nand_pinmux_setup(void)
{
unsigned int pin;
- for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(6); pin++)
- sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
- for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(22); pin++)
+ for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
+#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
+ for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
+#endif
+ /* sun4i / sun7i do have a PC23, but it is not used for nand,
+ * only sun7i has a PC24 */
+#ifdef CONFIG_MACH_SUN7I
sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
+#endif
}
static void nand_clock_setup(void)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
+#ifdef CONFIG_MACH_SUN9I
+ setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
+#else
+ setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
+#endif
setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
}
int power_failed = 0;
unsigned long ramsize;
-#ifdef CONFIG_AXP152_POWER
- power_failed = axp152_init();
- power_failed |= axp152_set_dcdc2(1400);
- power_failed |= axp152_set_dcdc3(1500);
- power_failed |= axp152_set_dcdc4(1250);
- power_failed |= axp152_set_ldo2(3000);
+#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER
+ power_failed = axp_init();
+
+#ifdef CONFIG_AXP221_POWER
+ power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
#endif
-#ifdef CONFIG_AXP209_POWER
- power_failed |= axp209_init();
- power_failed |= axp209_set_dcdc2(1400);
- power_failed |= axp209_set_dcdc3(1250);
- power_failed |= axp209_set_ldo2(3000);
- power_failed |= axp209_set_ldo3(2800);
- power_failed |= axp209_set_ldo4(2800);
+ power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
+ power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
+#ifndef CONFIG_AXP209_POWER
+ power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
#endif
#ifdef CONFIG_AXP221_POWER
- power_failed = axp221_init();
- power_failed |= axp221_set_dcdc1(CONFIG_AXP221_DCDC1_VOLT);
- power_failed |= axp221_set_dcdc2(CONFIG_AXP221_DCDC2_VOLT);
- power_failed |= axp221_set_dcdc3(1200); /* VDD-CPU */
-#ifdef CONFIG_MACH_SUN6I
- power_failed |= axp221_set_dcdc4(1200); /* A31:VDD-SYS */
-#else
- power_failed |= axp221_set_dcdc4(0); /* A23:unused */
+ power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
+#endif
+
+#ifdef CONFIG_AXP221_POWER
+ power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
+#endif
+ power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
+#ifndef CONFIG_AXP152_POWER
+ power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
#endif
- power_failed |= axp221_set_dcdc5(1500); /* VCC-DRAM */
- power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT);
- power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT);
- power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT);
- power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT);
- power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT);
- power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT);
+#ifdef CONFIG_AXP209_POWER
+ power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
#endif
+#ifdef CONFIG_AXP221_POWER
+ power_failed |= axp_set_dldo1(CONFIG_AXP_DLDO1_VOLT);
+ power_failed |= axp_set_dldo2(CONFIG_AXP_DLDO2_VOLT);
+ power_failed |= axp_set_dldo3(CONFIG_AXP_DLDO3_VOLT);
+ power_failed |= axp_set_dldo4(CONFIG_AXP_DLDO4_VOLT);
+ power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
+ power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
+ power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
+#endif
+#endif
printf("DRAM:");
ramsize = sunxi_dram_init();
printf(" %lu MiB\n", ramsize >> 20);
}
#endif
+#if !defined(CONFIG_SPL_BUILD)
+#include <asm/arch/spl.h>
+
+/*
+ * Check the SPL header for the "sunxi" variant. If found: parse values
+ * that might have been passed by the loader ("fel" utility), and update
+ * the environment accordingly.
+ */
+static void parse_spl_header(const uint32_t spl_addr)
+{
+ struct boot_file_head *spl = (void *)spl_addr;
+ if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) == 0) {
+ uint8_t spl_header_version = spl->spl_signature[3];
+ if (spl_header_version == SPL_HEADER_VERSION) {
+ if (spl->fel_script_address)
+ setenv_hex("fel_scriptaddr",
+ spl->fel_script_address);
+ return;
+ }
+ printf("sunxi SPL version mismatch: expected %u, got %u\n",
+ SPL_HEADER_VERSION, spl_header_version);
+ }
+}
+#endif
+
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
uint8_t mac_addr[6];
int ret;
+#if !defined(CONFIG_SPL_BUILD)
+ setenv("fel_booted", NULL);
+ setenv("fel_scriptaddr", NULL);
+ /* determine if we are running in FEL mode */
+ if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */
+ setenv("fel_booted", "1");
+ parse_spl_header(SPL_ADDR);
+ }
+#endif
+
ret = sunxi_get_sid(sid);
if (ret == 0 && sid[0] != 0 && sid[3] != 0) {
if (!getenv("ethaddr")) {