*/
#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
#include <asm/io.h>
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
#include <asm/arch/gpio.h>
-#include <dm/platdata.h>
+#include <asm/arch/fmc.h>
#include <dm/platform_data/serial_stm32x7.h>
#include <asm/arch/stm32_periph.h>
#include <asm/arch/stm32_defs.h>
+#include <asm/arch/syscfg.h>
+#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
-const struct stm32_gpio_ctl gpio_ctl_gpout = {
- .mode = STM32_GPIO_MODE_OUT,
- .otype = STM32_GPIO_OTYPE_PP,
- .speed = STM32_GPIO_SPEED_50M,
- .pupd = STM32_GPIO_PUPD_NO,
- .af = STM32_GPIO_AF0
-};
-
-const struct stm32_gpio_ctl gpio_ctl_usart = {
- .mode = STM32_GPIO_MODE_AF,
- .otype = STM32_GPIO_OTYPE_PP,
- .speed = STM32_GPIO_SPEED_50M,
- .pupd = STM32_GPIO_PUPD_UP,
- .af = STM32_GPIO_AF7
-};
-
-static const struct stm32_gpio_dsc usart_gpio[] = {
- {STM32_GPIO_PORT_A, STM32_GPIO_PIN_9}, /* TX */
- {STM32_GPIO_PORT_B, STM32_GPIO_PIN_7}, /* RX */
-};
-
-int uart_setup_gpio(void)
+int get_memory_base_size(fdt_addr_t *mr_base, fdt_addr_t *mr_size)
{
- int i;
- int rv = 0;
-
- clock_setup(GPIO_A_CLOCK_CFG);
- clock_setup(GPIO_B_CLOCK_CFG);
- for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) {
- rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart);
- if (rv)
- goto out;
+ int mr_node;
+
+ mr_node = fdt_path_offset(gd->fdt_blob, "/memory");
+ if (mr_node < 0)
+ return mr_node;
+ *mr_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, mr_node,
+ "reg", 0, mr_size, false);
+ debug("mr_base = %lx, mr_size= %lx\n", *mr_base, *mr_size);
+
+ return 0;
+}
+int dram_init(void)
+{
+ int rv;
+ fdt_addr_t mr_base, mr_size;
+
+#ifndef CONFIG_SUPPORT_SPL
+ struct udevice *dev;
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv) {
+ debug("DRAM init failed: %d\n", rv);
+ return rv;
}
-out:
+#endif
+ rv = get_memory_base_size(&mr_base, &mr_size);
+ if (rv)
+ return rv;
+ gd->ram_size = mr_size;
+ gd->ram_top = mr_base;
+
return rv;
}
-static const struct stm32x7_serial_platdata serial_platdata = {
- .base = (struct stm32_usart *)USART1_BASE,
- .clock = CONFIG_SYS_CLK_FREQ,
-};
+int dram_init_banksize(void)
+{
+ fdt_addr_t mr_base, mr_size;
+ get_memory_base_size(&mr_base, &mr_size);
+ /*
+ * Fill in global info with description of SRAM configuration
+ */
+ gd->bd->bi_dram[0].start = mr_base;
+ gd->bd->bi_dram[0].size = mr_size;
-U_BOOT_DEVICE(stm32x7_serials) = {
- .name = "serial_stm32x7",
- .platdata = &serial_platdata,
-};
+ return 0;
+}
-u32 get_board_rev(void)
+#ifdef CONFIG_ETH_DESIGNWARE
+static int stmmac_setup(void)
{
+ clock_setup(SYSCFG_CLOCK_CFG);
+ /* Set >RMII mode */
+ STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
+ clock_setup(STMMAC_CLOCK_CFG);
+
return 0;
}
int board_early_init_f(void)
{
- int res;
-
- res = uart_setup_gpio();
- clock_setup(USART1_CLOCK_CFG);
- if (res)
- return res;
+ stmmac_setup();
return 0;
}
+#endif
-int board_init(void)
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ debug("SPL: booting kernel\n");
+ /* break into full u-boot on 'c' */
+ return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+int spl_dram_init(void)
+{
+ struct udevice *dev;
+ int rv;
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv)
+ debug("DRAM init failed: %d\n", rv);
+ return rv;
+}
+void spl_board_init(void)
+{
+ spl_dram_init();
+ preloader_console_init();
+ arch_cpu_init(); /* to configure mpu for sdram rw permissions */
+}
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_XIP;
+}
+
+#endif
+u32 get_board_rev(void)
+{
return 0;
}
-int dram_init(void)
+int board_late_init(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
- gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
+ struct gpio_desc gpio = {};
+ int node;
+
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,led1");
+ if (node < 0)
+ return -1;
+
+ gpio_request_by_name_nodev(offset_to_ofnode(node), "led-gpio", 0, &gpio,
+ GPIOD_IS_OUT);
+
+ if (dm_gpio_is_valid(&gpio)) {
+ dm_gpio_set_value(&gpio, 0);
+ mdelay(10);
+ dm_gpio_set_value(&gpio, 1);
+ }
- gd->ram_size = CONFIG_SYS_RAM_SIZE;
+ /* read button 1*/
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,button1");
+ if (node < 0)
+ return -1;
+
+ gpio_request_by_name_nodev(offset_to_ofnode(node), "button-gpio", 0,
+ &gpio, GPIOD_IS_IN);
+
+ if (dm_gpio_is_valid(&gpio)) {
+ if (dm_gpio_get_value(&gpio))
+ puts("usr button is at HIGH LEVEL\n");
+ else
+ puts("usr button is at LOW LEVEL\n");
+ }
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
return 0;
}
projects / platform / kernel / u-boot.git / blobdiff