Merge git://git.denx.de/u-boot-rockchip

[platform/kernel/u-boot.git] / board / solidrun / mx6cuboxi / mx6cuboxi.c

diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index eab92f1..fc37f1e 100644 (file)
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -25,12 +25,15 @@
 #include <asm/imx-common/video.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
+#include <malloc.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <spl.h>
+#include <usb.h>
+#include <usb/ehci-fsl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -52,6 +55,7 @@ DECLARE_GLOBAL_DATA_PTR;
        PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
 
 #define ETH_PHY_RESET  IMX_GPIO_NR(4, 15)
+#define USB_H1_VBUS    IMX_GPIO_NR(1, 0)
 
 int dram_init(void)
 {
@@ -79,6 +83,10 @@ static iomux_v3_cfg_t const hb_cbi_sense[] = {
        IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04   | MUX_PAD_CTRL(UART_PAD_CTRL)),
 };
 
+static iomux_v3_cfg_t const usb_pads[] = {
+       IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
 static void setup_iomux_uart(void)
 {
        SETUP_IOMUX_PADS(uart1_pads);
@@ -126,6 +134,8 @@ static iomux_v3_cfg_t const enet_pads[] = {
        IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
        IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
        IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
+       IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
+       IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 };
 
 static void setup_iomux_enet(void)
@@ -145,11 +155,16 @@ int board_phy_config(struct phy_device *phydev)
        return 0;
 }
 
+/* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
+#define ETH_PHY_MASK   ((1 << 0x0) | (1 << 0x4))
+
 int board_eth_init(bd_t *bis)
 {
        struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+       struct mii_dev *bus;
+       struct phy_device *phydev;
 
-       int ret = enable_fec_anatop_clock(ENET_25MHZ);
+       int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
        if (ret)
                return ret;
 
@@ -158,7 +173,28 @@ int board_eth_init(bd_t *bis)
 
        setup_iomux_enet();
 
-       return cpu_eth_init(bis);
+       bus = fec_get_miibus(IMX_FEC_BASE, -1);
+       if (!bus)
+               return -EINVAL;
+
+       phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII);
+       if (!phydev) {
+               ret = -EINVAL;
+               goto free_bus;
+       }
+
+       debug("using phy at address %d\n", phydev->addr);
+       ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
+       if (ret)
+               goto free_phydev;
+
+       return 0;
+
+free_phydev:
+       free(phydev);
+free_bus:
+       free(bus);
+       return ret;
 }
 
 #ifdef CONFIG_VIDEO_IPUV3
@@ -253,6 +289,21 @@ static int setup_display(void)
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
 
+#ifdef CONFIG_USB_EHCI_MX6
+static void setup_usb(void)
+{
+       SETUP_IOMUX_PADS(usb_pads);
+}
+
+int board_ehci_hcd_init(int port)
+{
+       if (port == 1)
+               gpio_direction_output(USB_H1_VBUS, 1);
+
+       return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
        int ret = 0;
@@ -261,6 +312,10 @@ int board_early_init_f(void)
 #ifdef CONFIG_VIDEO_IPUV3
        ret = setup_display();
 #endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+       setup_usb();
+#endif
        return ret;
 }
 
@@ -481,7 +536,7 @@ static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
        .p0_mpdgctrl0 =    0x023C0224,
        .p0_mpdgctrl1 =    0x02000220,
        .p1_mpdgctrl0 =    0x02200220,
-       .p1_mpdgctrl1 =    0x02000220,
+       .p1_mpdgctrl1 =    0x02040208,
        .p0_mprddlctl =    0x44444846,
        .p1_mprddlctl =    0x4042463C,
        .p0_mpwrdlctl =    0x32343032,
@@ -560,6 +615,7 @@ static void spl_dram_init(int width)
                .bi_on = 1,     /* Bank interleaving enabled */
                .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
                .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
+               .ddr_type = DDR_TYPE_DDR3,
        };
 
        if (is_cpu_type(MXC_CPU_MX6D) || is_cpu_type(MXC_CPU_MX6Q))
@@ -572,7 +628,7 @@ static void spl_dram_init(int width)
        else if (is_cpu_type(MXC_CPU_MX6Q))
                mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
        else if (is_cpu_type(MXC_CPU_MX6DL))
-               mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
+               mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g);
        else if (is_cpu_type(MXC_CPU_MX6SOLO))
                mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
 }