Merge branch 'master' of git://git.denx.de/u-boot-arm

[platform/kernel/u-boot.git] / board / siemens / dxr2 / board.c

diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c
index 3a5e11d..2172379 100644 (file)
--- a/board/siemens/dxr2/board.c
+++ b/board/siemens/dxr2/board.c
@@ -144,6 +144,10 @@ struct ddr_data dxr2_ddr3_data = {
 
 struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
 };
+
+struct ctrl_ioregs dxr2_ddr3_ioregs = {
+};
+
        /* pass values from eeprom */
        dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
        dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
@@ -165,7 +169,13 @@ struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
        dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
        dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
 
-       config_ddr(DDR_PLL_FREQ, settings.ddr3.ioctr_val, &dxr2_ddr3_data,
+       dxr2_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
+       dxr2_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
+       dxr2_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
+       dxr2_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
+       dxr2_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
+
+       config_ddr(DDR_PLL_FREQ, &dxr2_ddr3_ioregs, &dxr2_ddr3_data,
                   &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
 }
 
@@ -188,7 +198,7 @@ static struct cpsw_slave_data cpsw_slaves[] = {
        {
                .slave_reg_ofs  = 0x208,
                .sliver_reg_ofs = 0xd80,
-               .phy_id         = 0,
+               .phy_addr       = 0,
                .phy_if         = PHY_INTERFACE_MODE_MII,
        },
 };
@@ -222,6 +232,13 @@ int board_eth_init(bd_t *bis)
 
        factoryset_setenv();
 
+       /* Reset SMSC LAN9303 switch for default configuration */
+       gpio_request(GPIO_LAN9303_NRST, "nRST");
+       gpio_direction_output(GPIO_LAN9303_NRST, 0);
+       /* assert active low reset for 200us */
+       udelay(200);
+       gpio_set_value(GPIO_LAN9303_NRST, 1);
+
        /* Set rgmii mode and enable rmii clock to be sourced from chip */
        writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);