#include <command.h>
#include "karef.h"
#include "karef_version.h"
+#include <timestamp.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <spd_sdram.h>
#include <i2c.h>
#include "../common/sb_common.h"
#include "../common/ppc440gx_i2c.h"
+#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
+ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
+#include <net.h>
+#endif
void fpga_init (void);
ppc440_gpio_regs_t *gpio_regs;
/* Enable GPIO interrupts */
- mtsdr(sdr_pfc0, 0x00103E00);
+ mtsdr(SDR0_PFC0, 0x00103E00);
/* Setup access for LEDs, and system topology info */
- gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
+ gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
/*--------------------------------------------------------------------+
| Initialize EBC CONFIG
+-------------------------------------------------------------------*/
- mtebc(xbcfg,
+ mtebc(EBC0_CFG,
EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
/*--------------------------------------------------------------------+
| 1/2 MB FLASH. Initialize bank 0 with default values.
+-------------------------------------------------------------------*/
- mtebc(pb0ap,
+ mtebc(PB0AP,
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
- mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
+ mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
/*--------------------------------------------------------------------+
| 8KB NVRAM/RTC. Initialize bank 1 with default values.
+-------------------------------------------------------------------*/
- mtebc(pb1ap,
+ mtebc(PB1AP,
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
- mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
+ mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
/*--------------------------------------------------------------------+
| Compact Flash, uses 2 Chip Selects (2 & 6)
+-------------------------------------------------------------------*/
- mtebc(pb2ap,
+ mtebc(PB2AP,
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
- mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
+ mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
/*--------------------------------------------------------------------+
| KaRef Scan FPGA. Initialize bank 3 with default values.
+-------------------------------------------------------------------*/
- mtebc(pb5ap,
+ mtebc(PB5AP,
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
- mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
+ mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48200000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
/*--------------------------------------------------------------------+
| MAC A & B for Kamino. OFEM FPGA decodes the addresses
| Initialize bank 4 with default values.
+-------------------------------------------------------------------*/
- mtebc(pb4ap,
+ mtebc(PB4AP,
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
- mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
+ mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) |
EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
/*--------------------------------------------------------------------+
| OFEM FPGA Initialize bank 5 with default values.
+-------------------------------------------------------------------*/
- mtebc(pb3ap,
+ mtebc(PB3AP,
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
- mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) |
+ mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48400000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
/*--------------------------------------------------------------------+
| Compact Flash, uses 2 Chip Selects (2 & 6)
+-------------------------------------------------------------------*/
- mtebc(pb6ap,
+ mtebc(PB6AP,
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
- mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
+ mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
/*--------------------------------------------------------------------+
| BME-32. Initialize bank 7 with default values.
+-------------------------------------------------------------------*/
- mtebc(pb7ap,
+ mtebc(PB7AP,
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
- mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
+ mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
/*--------------------------------------------------------------------+
KAREF_FPGA_REGS_ST *karef_ps;
OFEM_FPGA_REGS_ST *ofem_ps;
- karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
- ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
+ karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
+ ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
scan_id = (unsigned char)((karef_ps->revision_ul &
SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
"Serial Number: %d\n", sernum);
printf ("%s\n", KAREF_U_BOOT_REL_STR);
- printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
+ printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
if (sbcommon_get_master()) {
printf("Slot 0 - Master\nSlave board");
if (sbcommon_secondary_present())
/* Fix the ack in the bme 32 */
udelay(5000);
- out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
+ out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
asm("eieio");
{
/* Turn on i2c bus 1 */
puts ("I2C1: ");
- i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
puts ("ready\n");
/* Turn on fans 3 & 4 */
{
unsigned short sernum;
char envstr[255];
+ uchar enetaddr[6];
KAREF_FPGA_REGS_ST *karef_ps;
OFEM_FPGA_REGS_ST *ofem_ps;
setenv("ubrelver", KAREF_U_BOOT_REL_STR);
memset(envstr, 0, 255);
- sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
+ sprintf (envstr, "Built %s %s by %s",
+ U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
setenv("bldstr", envstr);
saveenv();
}
if( getenv("fakeled")) {
- karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
- ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
+ karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
+ ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
setenv("bootdelay", "-1");
printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
}
+#ifdef CONFIG_HAS_ETH0
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+ board_get_enetaddr(0, enetaddr);
+ eth_setenv_enetaddr("ethaddr", enetaddr);
+ }
+#endif
+
+#ifdef CONFIG_HAS_ETH1
+ if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
+ board_get_enetaddr(1, enetaddr);
+ eth_setenv_enetaddr("eth1addr", enetaddr);
+ }
+#endif
+
+#ifdef CONFIG_HAS_ETH2
+ if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
+ board_get_enetaddr(2, enetaddr);
+ eth_setenv_enetaddr("eth2addr", enetaddr);
+ }
+#endif
+
+#ifdef CONFIG_HAS_ETH3
+ if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
+ board_get_enetaddr(3, enetaddr);
+ eth_setenv_enetaddr("eth3addr", enetaddr);
+ }
+#endif
+
return (0);
}
{
KAREF_FPGA_REGS_ST *karef_ps;
/* TODO: ide reset */
- karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+ karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
if (on) {
karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
/* Ensure we have power all around */
udelay(500);
- karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+ karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
tmp =
SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
- ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
+ ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
ofem_ps->reset_ul = tmp;
ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
}
U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
- "kasetup - Set environment to factory defaults\n", NULL);
+ "Set environment to factory defaults", "");
U_BOOT_CMD(karecover, 1, 1, karefRecover,
- "karecover - Set environment to allow for fs recovery\n", NULL);
+ "Set environment to allow for fs recovery", "");