#include <config.h>
#include <version.h>
#include <asm/arch/cpu.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch/power.h>
-#include <asm/arch/watchdog.h>
-#include <asm/arch/interrupt.h>
+
+#define DEBUG_PM_C110
+#undef DEBUG_PM_C110
/*
* Register usages:
* r5 has zero always
* r7 has S5PC100 GPIO base, 0xE0300000
* r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
+ * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
*/
_TEXT_BASE:
.globl lowlevel_init
lowlevel_init:
- mov r9, lr
+ mov r11, lr
/* r5 has always zero */
mov r5, #0
- ldr r7, =S5PC100_GPIO_BASE(0)
- ldr r8, =S5PC100_GPIO_BASE(0)
+ ldr r7, =S5PC100_GPIO_BASE
+ ldr r8, =S5PC100_GPIO_BASE
/* Read CPU ID */
ldr r2, =S5PC1XX_PRO_ID
ldr r0, [r2]
and r0, r0, r1
cmp r0, r5
beq 100f
- ldr r8, =S5PC110_GPIO_BASE(0)
+ ldr r8, =S5PC110_GPIO_BASE
100:
- /* Turn on KEY_LED_ON [GPJ4(1)] */
+ /* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */
cmp r7, r8
- addeq r0, r8, #S5PC100_GPIO_J4_OFFSET
- addne r0, r8, #S5PC110_GPIO_J4_OFFSET
- ldr r1, [r0, #S5PC1XX_GPIO_CON_OFFSET]
+#ifndef DEBUG_PM_C110
+ addeq r0, r8, #0x280 @S5PC100_GPIO_J4_OFFSET
+ addne r0, r8, #0x2C0 @S5PC110_GPIO_J4_OFFSET
+ ldr r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET
bic r1, r1, #(0xf << 4) @ 1 * 4-bit
orr r1, r1, #(0x1 << 4)
- str r1, [r0, #S5PC1XX_GPIO_CON_OFFSET]
+ str r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET
- ldr r1, [r0, #S5PC1XX_GPIO_DAT_OFFSET]
+ ldr r1, [r0, #0x4] @S5PC1XX_GPIO_DAT_OFFSET
#ifdef CONFIG_ONENAND_IPL
orr r1, r1, #(1 << 1) @ 1 * 1-bit
#else
bic r1, r1, #(1 << 1)
#endif
- str r1, [r0, #S5PC1XX_GPIO_DAT_OFFSET]
+ str r1, [r0, #0x4] @S5PC1XX_GPIO_DAT_OFFSET
+#endif
/* IO retension release */
ldreq r0, =S5PC100_OTHERS @0xE0108200
/* Disable all interrupts (VIC0, VIC1 and VIC2) */
mvn r3, #0x0
- str r3, [r0, #VIC_INTENCLEAR_OFFSET]
- str r3, [r1, #VIC_INTENCLEAR_OFFSET]
- str r3, [r2, #VIC_INTENCLEAR_OFFSET]
+ str r3, [r0, #0x14] @INTENCLEAR
+ str r3, [r1, #0x14] @INTENCLEAR
+ str r3, [r2, #0x14] @INTENCLEAR
#ifndef CONFIG_ONENAND_IPL
/* Set all interrupts as IRQ */
- str r5, [r0, #VIC_INTSELECT_OFFSET]
- str r5, [r1, #VIC_INTSELECT_OFFSET]
- str r5, [r2, #VIC_INTSELECT_OFFSET]
+ str r5, [r0, #0xc] @INTSELECT
+ str r5, [r1, #0xc] @INTSELECT
+ str r5, [r2, #0xc] @INTSELECT
/* Pending Interrupt Clear */
- str r5, [r0, #VIC_INTADDRESS_OFFSET]
- str r5, [r1, #VIC_INTADDRESS_OFFSET]
- str r5, [r2, #VIC_INTADDRESS_OFFSET]
+ str r5, [r0, #0xf00] @INTADDRESS
+ str r5, [r1, #0xf00] @INTADDRESS
+ str r5, [r2, #0xf00] @INTADDRESS
#endif
#ifndef CONFIG_ONENAND_IPL
/* for UART */
bl uart_asm_init
- /* for TZPC */
- bl tzpc_asm_init
-
bl internal_ram_init
#endif
/* init system clock */
bl system_clock_init
+ /* Board detection to set proper memory configuration */
+ cmp r7, r8
+ moveq r9, #1 /* r9 has 1Gib default at s5pc100 */
+ movne r9, #2 /* r9 has 2Gib default at s5pc110 */
+ /* FIXME 1Gib detection: Limo Universal */
+ /* Check Limo Real board
+ * LR (suspend) LU J1B2
+ * 0x04 0x01 (0x01) 0x01 (0x01) 0x01 (0x01)
+ * 0x24 0x28 (0xA8) 0x28 (0x6A) 0x1C (0x1C)
+ * 0x44 0x00 (0xC7) 0x00 (0x47) 0x00 (0x47)
+ * 0x64 0x03 (0x1F) 0x07 (0x1F) 0x0f (0x0F)
+ *
+ * Check (0 << 3) at 0x64 at boot
+ * Check 0x47 at 0x44 at suspend
+ */
+ ldrne r2, =0xE0200C00
+ ldrne r1, [r2, #0x64]
+ and r1, r1, #(1 << 2)
+ cmp r1, #(1 << 2)
+ moveq r9, #1
+ ldr r1, [r2, #0x44]
+ cmp r1, #0x47
+ moveq r9, #1
+ /*
+ * Aquila Rev 0.5 : 4G3G1G x16 for Infineon ES3.1
+ * Aquila Rev 0.6 : 4G1G1G x32 for MSM6290
+ * Aquila Rev 0.7 : 4G2G1G x16 for Infineon ES3.1
+ * Aquila Rev 0.8 : 4G3G1G x16 for Infineon ES3.1
+ */
+ ldr r2, =0xE0200200
+ ldr r4, [r2, #0x48]
+ bic r1, r4, #(0xFF << 2) /* PULLUP_DISABLE: 4 * 2-bit */
+ str r1, [r2, #0x48]
+ /* For write completion */
+ nop
+ nop
+
+ ldr r3, [r2, #0x44]
+ and r1, r3, #(0xf << 1)
+ cmp r1, #(0x5 << 2)
+ moveq r9, #3
+ cmp r1, #(0x6 << 2)
+ moveq r9, #1
+ cmp r1, #(0x7 << 2)
+ moveq r9, #2
+ cmp r1, #(0x1 << 1)
+ moveq r9, #3
+ str r4, [r2, #0x48] /* Restore PULLUP configuration */
+
bl mem_ctrl_asm_init
/* OneNAND Sync Read Support at S5PC110 only
* VHF[3] : Very High Frequency Enable (Over 83MHz)
* HF[2] : High Frequency Enable (Over 66MHz)
*/
- ldrne r1, =0xF00C
+ cmp r7, r8
+ ldrne r1, =0xE00C
- ldrne r2, =0xB001E442
- strneh r1, [r2]
+ ldrne r0, =0xB001E442
+ strneh r1, [r0]
ldrne r0, =0xB0600000
strne r1, [r0, #0x100] @ ONENAND_IF_CTRL
ldreq r0, =S5PC100_RST_STAT
ldrne r0, =S5PC110_RST_STAT
ldr r1, [r0]
- bne 110f
- bic r1, r1, #0xfffffff7
- mov r2, #(1 << 3)
- b 200f
-110:
- bic r1, r1, #0xfffeffff
- mov r2, #(1 << 16)
-200:
+ biceq r1, r1, #0xfffffff7
+ moveq r2, #(1 << 3)
+ bicne r1, r1, #0xfffeffff
+ movne r2, #(1 << 16)
cmp r1, r2
bne 1f
wakeup:
+#ifdef DEBUG_PM_C110
+ mov r0, r8
+ ldr r1, =0x22222222
+ str r1, [r0, #0x0] @S5PC100_GPIO_A0_OFFSET
+ ldr r1, =0x00002222
+ str r1, [r0, #0x20] @S5PC100_GPIO_A1_OFFSET
+
+ /* UART_SEL MP0_5[7] at S5PC110 */
+ add r0, r8, #0x360 @S5PC110_GPIO_MP0_5_OFFSET
+ ldr r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET
+ bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
+ orr r1, r1, #(0x1 << 28) @ Output
+ str r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET
+
+ ldr r1, [r0, #0x8] @S5PC1XX_GPIO_PULL_OFFSET
+ bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
+ orr r1, r1, #(0x2 << 14) @ Pull-up enabled
+ str r1, [r0, #0x8] @S5PC1XX_GPIO_PULL_OFFSET
+
+ ldr r1, [r0, #0x4] @S5PC1XX_GPIO_DAT_OFFSET
+ orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
+ str r1, [r0, #0x4] @S5PC1XX_GPIO_DAT_OFFSET
+
+ ldr r0, =0xE2900000 @ S5PC110_PA_UART
+ orr r0, r0, #0x800
+ mov r1, #0x3
+ str r1, [r0, #0x000] @ ULCON
+ ldr r1, =0x245
+ str r1, [r0, #0x004] @ UCON
+ mov r1, #0x23
+ str r1, [r0, #0x028] @ UBRDIV
+ mov r1, #0x3
+ str r1, [r0, #0x02C] @ UDIVSLOT
+
+ mov r2, #'W'
+ strb r2, [r0, #0x020] @ UTXH
+1001:
+ ldrb r3, [r0, #0x010] @ UTRSTAT
+ tst r3, #(1 << 2)
+ beq 1001b
+#endif
+
+ /* turn off L2 cache */
+ bl l2_cache_disable
+
cmp r7, r8
- /* Clear wakeup status register */
- ldreq r0, =S5PC100_WAKEUP_STAT
- ldrne r0, =S5PC110_WAKEUP_STAT
- ldr r1, [r0]
- str r1, [r0]
+ ldreq r0, =0xC100
+ ldrne r0, =0xC110
+ /* invalidate L2 cache also */
+ bl invalidate_dcache
+
+ /* turn on L2 cache */
+ bl l2_cache_enable
+
+ cmp r7, r8
/* Load return address and jump to kernel */
ldreq r0, =S5PC100_INFORM0
ldrne r0, =S5PC110_INFORM0
mov pc, r1
nop
nop
+#else
+ cmp r7, r8
+ /* Clear wakeup status register */
+ ldreq r0, =S5PC100_WAKEUP_STAT
+ ldrne r0, =S5PC110_WAKEUP_STAT
+ ldr r1, [r0]
+ str r1, [r0]
#endif
1:
- mov lr, r9
+ mov lr, r11
mov pc, lr
/*
cmp r7, r8
bne 110f
100:
+#ifndef DEBUG_PM_C110
/* Set Lock Time */
ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
str r1, [r0, #0x000] @ S5PC100_APLL_LOCK
/* Set Source Clock */
ldr r1, =0x00001111 @ A, M, E, HPLL Muxing
str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
-
+#endif
b 200f
110:
/* Set Clock divider */
/* Set Lock Time */
ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
str r1, [r0, #0x000] @ S5PC110_APLL_LOCK
- str r1, [r0, #0x010] @ S5PC110_MPLL_LOCK
- str r1, [r0, #0x018] @ S5PC110_EPLL_LOCK
+ str r1, [r0, #0x008] @ S5PC110_MPLL_LOCK
+ str r1, [r0, #0x010] @ S5PC110_EPLL_LOCK
str r1, [r0, #0x020] @ S5PC110_VPLL_LOCK
/* S5PC110_APLL_CON */
ldr r1, =0x829B0C01 @ 667MHz
str r1, [r0, #0x108]
/* S5PC110_EPLL_CON */
- ldr r1, =0x80600602 @ 96MHz
+ ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2
str r1, [r0, #0x110]
/* S5PC110_VPLL_CON */
ldr r1, =0x806C0603 @ 54MHz
str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
/* OneDRAM(DMC0) clock setting */
- ldr r1, =0x01000000
- str r1, [r0, #0x218]
- ldr r1, =0x30000000
- str r1, [r0, #0x318]
-
- ldr r1, =0x00909000
- str r1, [r0, #0x500]
+ ldr r1, =0x01000000 @ ONEDRAM_SEL[25:24] 1 SCLKMPLL
+ str r1, [r0, #0x218] @ S5PC110_CLK_SRC6
+ ldr r1, =0x30000000 @ ONEDRAM_RATIO[31:28] 3 + 1
+ str r1, [r0, #0x318] @ S5PC110_CLK_DIV6
+
+ /* XCLKOUT = XUSBXTI 24MHz */
+ add r2, r0, #0xE000 @ S5PC110_OTHERS
+ ldr r1, [r2]
+ orr r1, r1, #(0x3 << 8) @ CLKOUT[9:8] 3 XUSBXTI
+ str r1, [r2]
+
+ /* CLK_IP0 */
+ ldr r1, =0x8fefeeb @ DMC[1:0] PDMA0[3] IMEM[5]
+ str r1, [r0, #0x460] @ S5PC110_CLK_IP0
+
+ /* CLK_IP1 */
+ ldr r1, =0xe9fdf0f9 @ FIMD[0] USBOTG[16]
+ @ NANDXL[24]
+ str r1, [r0, #0x464] @ S5PC110_CLK_IP1
+
+ /* CLK_IP2 */
+ ldr r1, =0xf75f7fc @ CORESIGHT[8] MODEM[9]
+ @ HOSTIF[10] HSMMC0[16]
+ @ HSMMC2[18] VIC[27:24]
+ str r1, [r0, #0x468] @ S5PC110_CLK_IP2
+
+ /* CLK_IP3 */
+ ldr r1, =0x8edf038c @ I2C[8:6]
+ @ SYSTIMER[16] UART0[17]
+ @ UART1[18] UART2[19]
+ @ UART3[20] WDT[22]
+ @ PWM[23] GPIO[26] SYSCON[27]
+ str r1, [r0, #0x46c] @ S5PC110_CLK_IP3
+
+ /* CLK_IP4 */
+ ldr r1, =0xfffffff1 @ CHIP_ID[0] TZPC[8:5]
+ str r1, [r0, #0x470] @ S5PC110_CLK_IP3
200:
/* wait at least 200us to stablize all clock */
/* set GPIO to enable UART0-UART4 */
mov r0, r8
ldr r1, =0x22222222
- str r1, [r0, #S5PC100_GPIO_A0_OFFSET] @ GPA0_CON
+ str r1, [r0, #0x0] @S5PC100_GPIO_A0_OFFSET
ldr r1, =0x00002222
- str r1, [r0, #S5PC100_GPIO_A1_OFFSET] @ GPA1_CON
+ str r1, [r0, #0x20] @S5PC100_GPIO_A1_OFFSET
/* Check S5PC100 */
cmp r7, r8
bne 110f
+#ifndef DEBUG_PM_C110
/* UART_SEL GPK0[5] at S5PC100 */
- add r0, r8, #S5PC100_GPIO_K0_OFFSET
- ldr r1, [r0, #S5PC1XX_GPIO_CON_OFFSET]
+ add r0, r8, #0x2A0 @S5PC100_GPIO_K0_OFFSET
+ ldr r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET
bic r1, r1, #(0xf << 20) @ 20 = 5 * 4-bit
orr r1, r1, #(0x1 << 20) @ Output
- str r1, [r0, #S5PC1XX_GPIO_CON_OFFSET]
+ str r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET
- ldr r1, [r0, #S5PC1XX_GPIO_PULL_OFFSET]
+ ldr r1, [r0, #0x8] @S5PC1XX_GPIO_PULL_OFFSET
bic r1, r1, #(0x3 << 10) @ 10 = 5 * 2-bit
orr r1, r1, #(0x2 << 10) @ Pull-up enabled
- str r1, [r0, #S5PC1XX_GPIO_PULL_OFFSET]
+ str r1, [r0, #0x8] @S5PC1XX_GPIO_PULL_OFFSET
- ldr r1, [r0, #S5PC1XX_GPIO_DAT_OFFSET]
+ ldr r1, [r0, #0x4] @S5PC1XX_GPIO_DAT_OFFSET
orr r1, r1, #(1 << 5) @ 5 = 5 * 1-bit
- str r1, [r0, #S5PC1XX_GPIO_DAT_OFFSET]
+ str r1, [r0, #0x4] @S5PC1XX_GPIO_DAT_OFFSET
+#endif
b 200f
110:
/*
* 0xE020'0360 is reserved address at S5PC100
*/
/* UART_SEL MP0_5[7] at S5PC110 */
- add r0, r8, #S5PC110_GPIO_MP0_5_OFFSET
- ldr r1, [r0, #S5PC1XX_GPIO_CON_OFFSET]
+ add r0, r8, #0x360 @S5PC110_GPIO_MP0_5_OFFSET
+ ldr r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET
bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
orr r1, r1, #(0x1 << 28) @ Output
- str r1, [r0, #S5PC1XX_GPIO_CON_OFFSET]
+ str r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET
- ldr r1, [r0, #S5PC1XX_GPIO_PULL_OFFSET]
+ ldr r1, [r0, #0x8] @S5PC1XX_GPIO_PULL_OFFSET
bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
orr r1, r1, #(0x2 << 14) @ Pull-up enabled
- str r1, [r0, #S5PC1XX_GPIO_PULL_OFFSET]
+ str r1, [r0, #0x8] @S5PC1XX_GPIO_PULL_OFFSET
- ldr r1, [r0, #S5PC1XX_GPIO_DAT_OFFSET]
+ ldr r1, [r0, #0x4] @S5PC1XX_GPIO_DAT_OFFSET
orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
- str r1, [r0, #S5PC1XX_GPIO_DAT_OFFSET]
+ str r1, [r0, #0x4] @S5PC1XX_GPIO_DAT_OFFSET
200:
mov pc, lr
-
-/*
- * tzpc_asm_init: Initialize TZPC
- */
-tzpc_asm_init:
- cmp r7, r8
- ldreq r0, =0xE3800000 @ TZPC0
- ldrne r0, =0xF1500000 @ TZPC0
- mov r1, #0x0
- str r1, [r0]
- mov r1, #0xff
- str r1, [r0, #0x804]
- str r1, [r0, #0x810]
- str r1, [r0, #0x81C]
-
- ldreq r0, =0xE2800000 @ TZPC1
- ldrne r0, =0xFAD00000 @ TZPC1
- str r1, [r0, #0x804]
- str r1, [r0, #0x810]
- str r1, [r0, #0x81C]
-
- ldreq r0, =0xE2900000 @ TZPC2
- ldrne r0, =0xE0600000 @ TZPC2
- str r1, [r0, #0x804]
- str r1, [r0, #0x810]
- str r1, [r0, #0x81C]
- str r1, [r0, #0x828]
-
- ldrne r0, =0xE1C00000 @ TZPC3 S5PC110 only
- strne r1, [r0, #0x804]
- strne r1, [r0, #0x810]
- strne r1, [r0, #0x81C]
-
- mov pc, lr
#endif
projects / kernel / u-boot.git / blobdiff