s5pc110: fix wrong PLL_LOCK offset

[kernel/u-boot.git] / board / samsung / universal / lowlevel_init.S

diff --git a/board/samsung/universal/lowlevel_init.S b/board/samsung/universal/lowlevel_init.S
index 8bcbbaa..a4353e8 100644 (file)
--- a/board/samsung/universal/lowlevel_init.S
+++ b/board/samsung/universal/lowlevel_init.S
@@ -26,11 +26,8 @@
 #include <config.h>
 #include <version.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/mem.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/power.h>
-#include <asm/arch/watchdog.h>
-#include <asm/arch/interrupt.h>
 
 #define DEBUG_PM_C110
 #undef DEBUG_PM_C110
@@ -114,20 +111,20 @@ lowlevel_init:
 
        /* Disable all interrupts (VIC0, VIC1 and VIC2) */
        mvn     r3, #0x0
-       str     r3, [r0, #VIC_INTENCLEAR_OFFSET]
-       str     r3, [r1, #VIC_INTENCLEAR_OFFSET]
-       str     r3, [r2, #VIC_INTENCLEAR_OFFSET]
+       str     r3, [r0, #0x14]                         @INTENCLEAR
+       str     r3, [r1, #0x14]                         @INTENCLEAR
+       str     r3, [r2, #0x14]                         @INTENCLEAR
 
 #ifndef CONFIG_ONENAND_IPL
        /* Set all interrupts as IRQ */
-       str     r5, [r0, #VIC_INTSELECT_OFFSET]
-       str     r5, [r1, #VIC_INTSELECT_OFFSET]
-       str     r5, [r2, #VIC_INTSELECT_OFFSET]
+       str     r5, [r0, #0xc]                          @INTSELECT
+       str     r5, [r1, #0xc]                          @INTSELECT
+       str     r5, [r2, #0xc]                          @INTSELECT
 
        /* Pending Interrupt Clear */
-       str     r5, [r0, #VIC_INTADDRESS_OFFSET]
-       str     r5, [r1, #VIC_INTADDRESS_OFFSET]
-       str     r5, [r2, #VIC_INTADDRESS_OFFSET]
+       str     r5, [r0, #0xf00]                        @INTADDRESS
+       str     r5, [r1, #0xf00]                        @INTADDRESS
+       str     r5, [r2, #0xf00]                        @INTADDRESS
 #endif
 
 #ifndef CONFIG_ONENAND_IPL
@@ -145,7 +142,7 @@ lowlevel_init:
        cmp     r7, r8
        moveq   r9, #1          /* r9 has 1Gib default at s5pc100 */
        movne   r9, #2          /* r9 has 2Gib default at s5pc110 */
-       /* FIXME 1Gib detection: Universal, Limo Universal */
+       /* FIXME 1Gib detection: Limo Universal */
        /* Check Limo Real board
         *      LR (suspend)    LU              J1B2
         * 0x04 0x01 (0x01)     0x01 (0x01)     0x01 (0x01)
@@ -164,6 +161,31 @@ lowlevel_init:
        ldr     r1, [r2, #0x44]
        cmp     r1, #0x47
        moveq   r9, #1
+       /*
+        * Aquila Rev 0.5 : 4G3G1G x16 for Infineon ES3.1
+        * Aquila Rev 0.6 : 4G1G1G x32 for MSM6290
+        * Aquila Rev 0.7 : 4G2G1G x16 for Infineon ES3.1
+        * Aquila Rev 0.8 : 4G3G1G x16 for Infineon ES3.1
+        */
+       ldr     r2, =0xE0200200
+       ldr     r4, [r2, #0x48]
+       bic     r1, r4, #(0xFF << 2)    /* PULLUP_DISABLE: 4 * 2-bit */
+       str     r1, [r2, #0x48]
+       /* For write completion */
+       nop
+       nop
+
+       ldr     r3, [r2, #0x44]
+       and     r1, r3, #(0xf << 1)
+       cmp     r1, #(0x5 << 2)
+       moveq   r9, #3
+       cmp     r1, #(0x6 << 2)
+       moveq   r9, #1
+       cmp     r1, #(0x7 << 2)
+       moveq   r9, #2
+       cmp     r1, #(0x1 << 1)
+       moveq   r9, #3
+       str     r4, [r2, #0x48]         /* Restore PULLUP configuration */
 
        bl      mem_ctrl_asm_init
 
@@ -174,6 +196,7 @@ lowlevel_init:
         * VHF[3]       : Very High Frequency Enable (Over 83MHz)
         * HF[2]        : High Frequency Enable (Over 66MHz)
         */
+       cmp     r7, r8
        ldrne   r1, =0xE00C
 
        ldrne   r0, =0xB001E442
@@ -356,8 +379,8 @@ system_clock_init:
        /* Set Lock Time */
        ldr     r1, =0xe10                      @ Locktime : 0xe10 = 3600
        str     r1, [r0, #0x000]                @ S5PC110_APLL_LOCK
-       str     r1, [r0, #0x010]                @ S5PC110_MPLL_LOCK
-       str     r1, [r0, #0x018]                @ S5PC110_EPLL_LOCK
+       str     r1, [r0, #0x008]                @ S5PC110_MPLL_LOCK
+       str     r1, [r0, #0x010]                @ S5PC110_EPLL_LOCK
        str     r1, [r0, #0x020]                @ S5PC110_VPLL_LOCK
 
        /* S5PC110_APLL_CON */
@@ -389,6 +412,33 @@ system_clock_init:
        orr     r1, r1, #(0x3 << 8)             @ CLKOUT[9:8] 3 XUSBXTI
        str     r1, [r2]
 
+       /* CLK_IP0 */
+       ldr     r1, =0x8fefeeb                  @ DMC[1:0] PDMA0[3] IMEM[5]
+       str     r1, [r0, #0x460]                @ S5PC110_CLK_IP0
+
+       /* CLK_IP1 */
+       ldr     r1, =0xe9fdf0f9                 @ FIMD[0] USBOTG[16]
+                                               @ NANDXL[24]
+       str     r1, [r0, #0x464]                @ S5PC110_CLK_IP1
+
+       /* CLK_IP2 */
+       ldr     r1, =0xf75f7fc                  @ CORESIGHT[8] MODEM[9]
+                                               @ HOSTIF[10] HSMMC0[16]
+                                               @ HSMMC2[18] VIC[27:24]
+       str     r1, [r0, #0x468]                @ S5PC110_CLK_IP2
+
+       /* CLK_IP3 */
+       ldr     r1, =0x8edf038c                 @ I2C[8:6]
+                                               @ SYSTIMER[16] UART0[17]
+                                               @ UART1[18] UART2[19]
+                                               @ UART3[20] WDT[22]
+                                               @ PWM[23] GPIO[26] SYSCON[27]
+       str     r1, [r0, #0x46c]                @ S5PC110_CLK_IP3
+
+       /* CLK_IP4 */
+       ldr     r1, =0xfffffff1                 @ CHIP_ID[0] TZPC[8:5]
+       str     r1, [r0, #0x470]                @ S5PC110_CLK_IP3
+
 200:
        /* wait at least 200us to stablize all clock */
        mov     r2, #0x10000