* MA 02111-1307 USA
*/
-#include <asm/u-boot.h>
#include <common.h>
+#include <asm/u-boot.h>
#include <ioports.h>
#include <mpc8260.h>
#include <i2c.h>
#include <spi.h>
+#include <command.h>
#ifdef CONFIG_SHOW_BOOT_PROGRESS
#include <status_led.h>
#endif
+#ifdef CONFIG_ETHER_LOOPBACK_TEST
+extern void eth_loopback_test(void);
+#endif /* CONFIG_ETHER_LOOPBACK_TEST */
+
+extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
#include "clkinit.h"
#include "ioconfig.h" /* I/O configuration table */
/* ------------------------------------------------------------------------- */
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar c = 0;
- volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8);
- uint psdmr = CFG_PSDMR;
+ volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8);
+ uint psdmr = CONFIG_SYS_PSDMR;
int i;
uint psrt = 14; /* for no SPD */
uint chipselects = 1; /* for no SPD */
- uint sdram_size = CFG_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */
- uint or = CFG_OR2_PRELIM; /* for no SPD */
+ uint sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */
+ uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */
#ifdef SDRAM_SPD_ADDR
uint data_width;
uint rows;
/* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
if(caslatency < 2) {
- printf("CL was %d, forcing to 2\n", caslatency);
+ printf("WARNING: CL was %d, forcing to 2\n", caslatency);
caslatency = 2;
}
if(rows > 14) {
- printf("This doesn't look good, rows = %d, should be <= 14\n", rows);
+ printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n", rows);
rows = 14;
}
if(cols > 11) {
- printf("This doesn't look good, columns = %d, should be <= 11\n", cols);
+ printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n", cols);
cols = 11;
}
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+ * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
*/
- memctl->memc_mptpr = CFG_MPTPR;
+ memctl->memc_mptpr = CONFIG_SYS_MPTPR;
memctl->memc_psrt = psrt;
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
if(chipselects > 1) {
ramaddr += sdram_size;
- memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size;
+ memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size;
memctl->memc_or3 = or;
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
/*
* Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization.
*/
- volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */);
- volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
+ volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */);
+ volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
int reg; /* I2C register value */
char *ep; /* Environment pointer */
int sample_128x; /* Use 128/4 clocking for the ADC/DAC */
int right_just; /* Is the data to the DAC right justified? */
int mclk_divide; /* MCLK Divide */
+ int quiet; /* Quiet or minimal output mode */
+
+ quiet = 0;
+ if ((ep = getenv("quiet")) != NULL) {
+ quiet = simple_strtol(ep, NULL, 10);
+ }
+ else {
+ setenv("quiet", "0");
+ }
/*
* SACSng custom initialization:
setenv("Daq128xSampling", "1");
}
- /* Display the ADC/DAC clocking information */
- Daq_Display_Clocks();
+ /*
+ * Display the ADC/DAC clocking information
+ */
+ if (!quiet) {
+ Daq_Display_Clocks();
+ }
/*
* Determine the DAC data justification
* 4) Enable address matching by setting the MSB in register 7
*/
- printf("Initializing the ADC...\n");
+ if (!quiet) {
+ printf("Initializing the ADC...\n");
+ }
udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */
iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */
* sending an I2C "start" sequence. When we bring the I2C back to
* the normal state, we send an I2C "stop" sequence.
*/
- printf("Initializing the DAC...\n");
+ if (!quiet) {
+ printf("Initializing the DAC...\n");
+ }
/*
* Bring the I2C clock and data lines low for initialization
I2C_DELAY;
I2C_TRISTATE;
- printf("\n");
+ if (!quiet) {
+ printf("\n");
+ }
+
+#ifdef CONFIG_ETHER_LOOPBACK_TEST
+ /*
+ * Run the Ethernet loopback test
+ */
+ eth_loopback_test ();
+#endif /* CONFIG_ETHER_LOOPBACK_TEST */
#ifdef CONFIG_SHOW_BOOT_PROGRESS
/*
void show_boot_progress (int status)
{
- if(status != -1) {
+ int i,j;
+ if(status > 0) {
last_boot_progress = status;
} else {
/*
- * Houston, we have a problem. Blink the last OK status which
- * indicates where things failed.
+ * If a specific failure code is given, flash this code
+ * else just use the last success code we've seen
*/
- status_led_set(STATUS_LED_RED, STATUS_LED_ON);
- flash_code(last_boot_progress, 5, 3);
- udelay(1000000);
- status_led_set(STATUS_LED_RED, STATUS_LED_BLINKING);
+ if(status < -1)
+ last_boot_progress = -status;
+
+ /*
+ * Flash this code 5 times
+ */
+ for(j=0; j<5; j++) {
+ /*
+ * Houston, we have a problem.
+ * Blink the last OK status which indicates where things failed.
+ */
+ status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+ flash_code(last_boot_progress, 5, 3);
+
+ /*
+ * Delay 5 seconds between repetitions,
+ * with the fault LED blinking
+ */
+ for(i=0; i<5; i++) {
+ status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
+ udelay(500000);
+ status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+ udelay(500000);
+ }
+ }
+
+ /*
+ * Reset the board to retry initialization.
+ */
+ do_reset (NULL, 0, 0, NULL);
}
}
#endif /* CONFIG_SHOW_BOOT_PROGRESS */
/*
* The following are used to control the SPI chip selects for the SPI command.
*/
-#if (CONFIG_COMMANDS & CFG_CMD_SPI)
+#if defined(CONFIG_CMD_SPI)
#define SPI_ADC_CS_MASK 0x00000800
#define SPI_DAC_CS_MASK 0x00001000
-void spi_adc_chipsel(int cs)
-{
- volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
+static const u32 cs_mask[] = {
+ SPI_ADC_CS_MASK,
+ SPI_DAC_CS_MASK,
+};
- if(cs)
- iopd->pdat &= ~SPI_ADC_CS_MASK; /* activate the chip select */
- else
- iopd->pdat |= SPI_ADC_CS_MASK; /* deactivate the chip select */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs < sizeof(cs_mask) / sizeof(cs_mask[0]);
}
-void spi_dac_chipsel(int cs)
+void spi_cs_activate(struct spi_slave *slave)
{
- volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
+ volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */);
- if(cs)
- iopd->pdat &= ~SPI_DAC_CS_MASK; /* activate the chip select */
- else
- iopd->pdat |= SPI_DAC_CS_MASK; /* deactivate the chip select */
+ iopd->pdat &= ~cs_mask[slave->cs];
}
-/*
- * The SPI command uses this table of functions for controlling the SPI
- * chip selects: it calls the appropriate function to control the SPI
- * chip selects.
- */
-spi_chipsel_type spi_chipsel[] = {
- spi_adc_chipsel,
- spi_dac_chipsel
-};
-int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */);
-#endif /* CFG_CMD_SPI */
+ iopd->pdat |= cs_mask[slave->cs];
+}
+
+#endif
#endif /* CONFIG_MISC_INIT_R */
projects / platform / kernel / u-boot.git / blobdiff