Merge tag 'u-boot-rockchip-20200501' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / board / renesas / salvator-x / salvator-x.c

diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index cb5228a..91c3728 100644 (file)
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -8,6 +8,7 @@
  */
 
 #include <common.h>
+#include <cpu_func.h>
 #include <malloc.h>
 #include <netdev.h>
 #include <dm.h>
@@ -27,25 +28,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define CPGWPCR        0xE6150904
-#define CPGWPR  0xE6150900
-
-#define CLK2MHZ(clk)   (clk / 1000 / 1000)
 void s_init(void)
 {
-       struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
-       struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
-
-       /* Watchdog init */
-       writel(0xA5A5A500, &rwdt->rwtcsra);
-       writel(0xA5A5A500, &swdt->swtcsra);
-
-       writel(0x5A5AFFFF, CPGWPR);
-       writel(0xA5A50000, CPGWPCR);
 }
 
-#define GSX_MSTP112            BIT(12) /* 3DG */
-#define SCIF2_MSTP310          BIT(10) /* SCIF2 */
 #define DVFS_MSTP926           BIT(26)
 #define HSUSB_MSTP704          BIT(4)  /* HSUSB */
 
@@ -53,17 +39,11 @@ int board_early_init_f(void)
 {
 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
        /* DVFS for reset */
-       mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+       mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
 #endif
        return 0;
 }
 
-/* SYSC */
-/* R/- 32 Power status register 2(3DG) */
-#define        SYSC_PWRSR2     0xE6180100
-/* -/W 32 Power resume control register 2 (3DG) */
-#define        SYSC_PWRONCR2   0xE618010C
-
 /* HSUSB block registers */
 #define HSUSB_REG_LPSTS                        0xE6590102
 #define HSUSB_REG_LPSTS_SUSPM_NORMAL   BIT(14)
@@ -73,25 +53,14 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-       u32 cpu_type = rmobile_get_cpu_type();
-
        /* adress of boot parameters */
        gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
 
-       if (cpu_type == RMOBILE_CPU_TYPE_R8A7795) {
-               /* GSX: force power and clock supply */
-               writel(0x0000001F, SYSC_PWRONCR2);
-               while (readl(SYSC_PWRSR2) != 0x000003E0)
-                       mdelay(20);
-
-               mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
-       }
-
        /* USB1 pull-up */
        setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
 
        /* Configure the HSUSB block */
-       mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+       mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
        /* Choice USB0SEL */
        clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
                        HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
@@ -101,21 +70,6 @@ int board_init(void)
        return 0;
 }
 
-int dram_init(void)
-{
-       if (fdtdec_setup_mem_size_base() != 0)
-               return -EINVAL;
-
-       return 0;
-}
-
-int dram_init_banksize(void)
-{
-       fdtdec_setup_memory_banksize();
-
-       return 0;
-}
-
 #define RST_BASE       0xE6160000
 #define RST_CA57RESCNT (RST_BASE + 0x40)
 #define RST_CA53RESCNT (RST_BASE + 0x44)
@@ -131,3 +85,25 @@ void reset_cpu(ulong addr)
        writel(RST_CODE, RST_CA57RESCNT);
 #endif
 }
+
+#ifdef CONFIG_MULTI_DTB_FIT
+int board_fit_config_name_match(const char *name)
+{
+       /* PRR driver is not available yet */
+       u32 cpu_type = rmobile_get_cpu_type();
+
+       if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) &&
+           !strcmp(name, "r8a77950-salvator-x-u-boot"))
+               return 0;
+
+       if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) &&
+           !strcmp(name, "r8a77960-salvator-x-u-boot"))
+               return 0;
+
+       if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) &&
+           !strcmp(name, "r8a77965-salvator-x-u-boot"))
+               return 0;
+
+       return -1;
+}
+#endif