#include <common.h>
-#include <asm/processor.h>
+#include <libfdt.h>
+#include <fdt_support.h>
#include <spd_sdram.h>
#include <ppc4xx_enet.h>
+#include <miiphy.h>
+#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f (void)
{
- unsigned long mfr;
-
- /*-------------------------------------------------------------------------+
- | Initialize EBC CONFIG
- +-------------------------------------------------------------------------*/
-#if 0
- mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
- EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
- EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
- EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
- EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
-#else
+ /*-------------------------------------------------------------------------
+ * Initialize EBC CONFIG
+ *-------------------------------------------------------------------------*/
mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK |
EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
-#endif
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
mtdcr (uic0sr, 0xffffffff); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
- mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
- mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
+ mtdcr (uic0pr, 0xfffffe03); /* per manual */
+ mtdcr (uic0tr, 0x01c00000); /* per manual */
mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic0sr, 0xffffffff); /* clear all */
mtdcr (uicb0pr, 0xfc000000); /* */
mtdcr (uicb0tr, 0x00000000); /* */
mtdcr (uicb0vr, 0x00000001); /* */
- mfsdr (sdr_mfr, mfr);
- mfr &= ~SDR0_MFR_ECS_MASK;
+
+ /* Setup shutdown/SSD empty interrupt as inputs */
+ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
+ out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
+
+ /* Setup GPIO/IRQ multiplexing */
+ mtsdr(sdr_pfc0, 0x01a33e00);
+
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ unsigned short reg;
+
+ /*
+ * Configure LED's of both Marvell 88E1111 PHY's
+ *
+ * This has to be done after the 4xx ethernet driver is loaded,
+ * so "last_stage_init()" is the right place.
+ */
+ miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, ®);
+ reg |= 0x0001;
+ miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg);
+ miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, ®);
+ reg |= 0x0001;
+ miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg);
return 0;
}
+static int board_rev(void)
+{
+ /* Setup as input */
+ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1));
+ out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1));
+
+ return (in32(GPIO0_IR) >> 16) & 0x3;
+}
+
int checkboard (void)
{
char *s = getenv ("serial#");
puts (", serial# ");
puts (s);
}
- putc ('\n');
+ printf(" (Rev. %d)\n", board_rev());
return (0);
}
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
- uint *pstart = (uint *) 0x00000000;
- uint *pend = (uint *) 0x08000000;
- uint *p;
-
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
- return 0;
-}
-#endif
-
/*************************************************************************
* pci_pre_init
*
* certain pre-initialization actions.
*
************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
return 1;
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
************************************************************************/
#if defined(CONFIG_PCI)
+
+static void wait_for_pci_ready(void)
+{
+ /*
+ * Configure EREADY as input
+ */
+ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY);
+ udelay(1000);
+
+ for (;;) {
+ if (in32(GPIO0_IR) & CFG_GPIO_EREADY)
+ return;
+ }
+
+}
+
int is_pci_host(struct pci_controller *hose)
{
- /* The ocotea board is always configured as host. */
- return(1);
+ wait_for_pci_ready();
+ return 1; /* return 1 for host controller */
}
#endif /* defined(CONFIG_PCI) */
}
#endif
-void board_reset(void)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
{
- /*
- * Initiate chip reset in debug control register DBCR
- */
- mtspr(dbcr0, 0x20000000);
+ u32 val[4];
+ int rc;
+
+ ft_cpu_setup(blob, bd);
+
+ /* Fixup NOR mapping */
+ val[0] = 0; /* chip select number */
+ val[1] = 0; /* always 0 */
+ val[2] = gd->bd->bi_flashstart;
+ val[3] = gd->bd->bi_flashsize;
+ rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
+ val, sizeof(val), 1);
+ if (rc)
+ printf("Unable to update property NOR mapping, err=%s\n",
+ fdt_strerror(rc));
}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
projects / platform / kernel / u-boot.git / blobdiff