Merge branch 'master' of git://git.denx.de/u-boot-spi

[platform/kernel/u-boot.git] / board / phytec / pcm051 / board.c

diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 55bc018..0cca8d7 100644 (file)
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -39,9 +39,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-#ifdef CONFIG_SPL_BUILD
-static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-#endif
 
 /* MII mode defines */
 #define MII_MODE_ENABLE                0x0
@@ -50,31 +47,11 @@ static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
-/* UART defines */
 #ifdef CONFIG_SPL_BUILD
-#define UART_RESET             (0x1 << 1)
-#define UART_CLK_RUNNING_MASK  0x1
-#define UART_SMART_IDLE_EN     (0x1 << 0x3)
 
 /* DDR RAM defines */
 #define DDR_CLK_MHZ            303 /* DDR_DPLL_MULT value */
 
-static void rtc32k_enable(void)
-{
-       struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
-
-       /*
-        * Unlock the RTC's registers.  For more details please see the
-        * RTC_SS section of the TRM.  In order to unlock we need to
-        * write these specific values (keys) in this order.
-        */
-       writel(0x83e70b13, &rtc->kick0r);
-       writel(0x95a4f1e0, &rtc->kick1r);
-
-       /* Enable the RTC 32K OSC by setting bits 3 and 6. */
-       writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
 static const struct ddr_data ddr3_data = {
        .datardsratio0 = MT41J256M8HX15E_RD_DQS,
        .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
@@ -104,7 +81,8 @@ static struct emif_regs ddr3_emif_reg_data = {
        .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
        .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
        .zq_config = MT41J256M8HX15E_ZQ_CFG,
-       .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY,
+       .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
+                               PHY_EN_DYN_PWRDN,
 };
 #endif
 
@@ -114,6 +92,15 @@ static struct emif_regs ddr3_emif_reg_data = {
 void s_init(void)
 {
        /*
+        * Save the boot parameters passed from romcode.
+        * We cannot delay the saving further than this,
+        * to prevent overwrites.
+        */
+#ifdef CONFIG_SPL_BUILD
+       save_omap_boot_params();
+#endif
+
+       /*
         * WDT1 is already running when the bootloader gets control
         * Disable it to avoid "random" resets
         */
@@ -131,22 +118,8 @@ void s_init(void)
        /* Enable RTC32K clock */
        rtc32k_enable();
 
-       /* UART softreset */
-       u32 regval;
-
        enable_uart0_pin_mux();
-
-       regval = readl(&uart_base->uartsyscfg);
-       regval |= UART_RESET;
-       writel(regval, &uart_base->uartsyscfg);
-       while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK)
-               != UART_CLK_RUNNING_MASK)
-               ;
-
-       /* Disable smart idle */
-       regval = readl(&uart_base->uartsyscfg);
-       regval |= UART_SMART_IDLE_EN;
-       writel(regval, &uart_base->uartsyscfg);
+       uart_soft_reset();
 
        gd = &gdata;
 
@@ -159,7 +132,7 @@ void s_init(void)
        enable_board_pin_mux();
 
        config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
-                       &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
+                       &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 #endif
 }
 
@@ -199,8 +172,8 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 };
 
 static struct cpsw_platform_data cpsw_data = {
-       .mdio_base              = AM335X_CPSW_MDIO_BASE,
-       .cpsw_base              = AM335X_CPSW_BASE,
+       .mdio_base              = CPSW_MDIO_BASE,
+       .cpsw_base              = CPSW_BASE,
        .mdio_div               = 0xff,
        .channels               = 8,
        .cpdma_reg_ofs          = 0x800,