ppc4xx: Big cleanup of PPC4xx defines

[platform/kernel/u-boot.git] / board / pcs440ep / pcs440ep.c

diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
index 9cc3f5b..f966d02 100644 (file)
--- a/board/pcs440ep/pcs440ep.c
+++ b/board/pcs440ep/pcs440ep.c
@@ -143,9 +143,9 @@ int board_early_init_f(void)
        /*--------------------------------------------------------------------
         * Setup the external bus controller/chip selects
         *-------------------------------------------------------------------*/
-       mtdcr(ebccfga, xbcfg);
-       reg = mfdcr(ebccfgd);
-       mtdcr(ebccfgd, reg | 0x04000000);       /* Set ATC */
+       mtdcr(EBC0_CFGADDR, EBC0_CFG);
+       reg = mfdcr(EBC0_CFGDATA);
+       mtdcr(EBC0_CFGDATA, reg | 0x04000000);  /* Set ATC */
 
        /*--------------------------------------------------------------------
         * GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c
@@ -174,10 +174,10 @@ int board_early_init_f(void)
        /*--------------------------------------------------------------------
         * Setup other serial configuration
         *-------------------------------------------------------------------*/
-       mfsdr(sdr_pci0, reg);
-       mtsdr(sdr_pci0, 0x80000000 | reg);      /* PCI arbiter enabled */
-       mtsdr(sdr_pfc0, 0x00000000);    /* Pin function: enable GPIO49-63 */
-       mtsdr(sdr_pfc1, 0x00048000);    /* Pin function: UART0 has 4 pins, select IRQ5 */
+       mfsdr(SDR0_PCI0, reg);
+       mtsdr(SDR0_PCI0, 0x80000000 | reg);     /* PCI arbiter enabled */
+       mtsdr(SDR0_PFC0, 0x00000000);   /* Pin function: enable GPIO49-63 */
+       mtsdr(SDR0_PFC1, 0x00048000);   /* Pin function: UART0 has 4 pins, select IRQ5 */
 
        return 0;
 }
@@ -444,8 +444,8 @@ int misc_init_r (void)
        load_ethaddr();
 
        /* Re-do sizing to get full correct info */
-       mtdcr(ebccfga, pb0cr);
-       pbcr = mfdcr(ebccfgd);
+       mtdcr(EBC0_CFGADDR, PB0CR);
+       pbcr = mfdcr(EBC0_CFGDATA);
        switch (gd->bd->bi_flashsize) {
        case 1 << 20:
                size_val = 0;
@@ -473,8 +473,8 @@ int misc_init_r (void)
                break;
        }
        pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-       mtdcr(ebccfga, pb0cr);
-       mtdcr(ebccfgd, pbcr);
+       mtdcr(EBC0_CFGADDR, PB0CR);
+       mtdcr(EBC0_CFGDATA, pbcr);
 
        /* adjust flash start and offset */
        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
@@ -571,35 +571,35 @@ int pci_pre_init(struct pci_controller *hose)
          | Set priority for all PLB3 devices to 0.
          | Set PLB3 arbiter to fair mode.
          +-------------------------------------------------------------------------*/
-       mfsdr(sdr_amp1, addr);
-       mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
-       addr = mfdcr(plb3_acr);
-       mtdcr(plb3_acr, addr | 0x80000000);
+       mfsdr(SD0_AMP1, addr);
+       mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
+       addr = mfdcr(PLB3_ACR);
+       mtdcr(PLB3_ACR, addr | 0x80000000);
 
        /*-------------------------------------------------------------------------+
          | Set priority for all PLB4 devices to 0.
          +-------------------------------------------------------------------------*/
-       mfsdr(sdr_amp0, addr);
-       mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
-       addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
-       mtdcr(plb4_acr, addr);
+       mfsdr(SD0_AMP0, addr);
+       mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
+       addr = mfdcr(PLB4_ACR) | 0xa0000000;    /* Was 0x8---- */
+       mtdcr(PLB4_ACR, addr);
 
        /*-------------------------------------------------------------------------+
          | Set Nebula PLB4 arbiter to fair mode.
          +-------------------------------------------------------------------------*/
        /* Segment0 */
-       addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
-       addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
-       addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
-       addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
-       mtdcr(plb0_acr, addr);
+       addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
+       addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
+       addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
+       addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
+       mtdcr(PLB0_ACR, addr);
 
        /* Segment1 */
-       addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
-       addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
-       addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
-       addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
-       mtdcr(plb1_acr, addr);
+       addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
+       addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
+       addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
+       addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
+       mtdcr(PLB1_ACR, addr);
 
        return 1;
 }
@@ -763,7 +763,7 @@ U_BOOT_CMD(
        "              0x02 = DIAG 2 on\n"
        "              0x04 = DIAG 3 on\n"
        "              0x08 = DIAG 4 on\n"
-       "              > 0x100 set the LED, who are on, to state blinking\n"
+       "              > 0x100 set the LED, who are on, to state blinking"
 );
 
 #if defined(CONFIG_SHA1_CHECK_UB_IMG)
@@ -823,7 +823,7 @@ U_BOOT_CMD(
        "calculate the SHA1 Sum",
        "address len [addr]  calculate the SHA1 sum [save at addr]\n"
        "     -p calculate the SHA1 sum from the U-Boot image in flash and print\n"
-       "     -c check the U-Boot image in flash\n"
+       "     -c check the U-Boot image in flash"
 );
 #endif