#include <asm/arch/mem.h>
#include <i2c.h>
#include <asm/mach-types.h>
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-#endif
- void wait_for_command_complete(unsigned int wd_base);
+DECLARE_GLOBAL_DATA_PTR;
+
+void wait_for_command_complete(unsigned int wd_base);
/*******************************************************
* Routine: delay
*****************************************/
int board_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gpmc_init(); /* in SRAM or SDRM, finish GPMC */
gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4; /* board id for linux */
***********************************************************/
void try_unlock_sram(void)
{
- int mode;
-
- /* if GP device unlock device SRAM for general use */
- mode = (__raw_readl(CONTROL_STATUS) & (BIT8|BIT9));
- if (mode == GP_DEVICE) {
- __raw_writel(0xFF, A_REQINFOPERM0);
- __raw_writel(0xCFDE, A_READPERM0);
- __raw_writel(0xCFDE, A_WRITEPERM0);
- }
-}
-
-/**********************************************************
- * Routine: try_unlock_sram()
- * Description: If chip is GP type, unlock the SRAM for
- * general use.
- ***********************************************************/
-void try_unlock_sram(void)
-{
/* if GP device unlock device SRAM for general use */
if (get_device_type() == GP_DEVICE) {
__raw_writel(0xFF, A_REQINFOPERM0);
/*******************************************************************
* Routine:ether_init
* Description: take the Ethernet controller out of reset and wait
- * for the EEPROM load to complete.
+ * for the EEPROM load to complete.
******************************************************************/
void ether_init (void)
{
**********************************************/
int dram_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
unsigned int size0=0,size1=0;
u32 mtype, btype, rev, cpu;
u8 chg_on = 0x5; /* enable charge of back up battery */
u8 vmode_on = 0x8C;
#define NOT_EARLY 0
- i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); /* need this a bit early */
+ i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* need this a bit early */
btype = get_board_type();
mtype = get_mem_type();
__raw_writel(v, CM_CLKSEL2_CORE);
__raw_writel(0x1, CM_CLKSEL_WKUP);
-#ifdef CFG_NS16550
+#ifdef CONFIG_SYS_NS16550
/* Enable UART1 clock */
func_clks |= BIT21;
if_clks |= BIT21;
}
}
}
-
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-void nand_init(void)
-{
- extern flash_info_t flash_info[];
-
- nand_probe(CFG_NAND_ADDR);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-
-#ifdef CFG_JFFS2_MEM_NAND
- flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id;
- flash_info[CFG_JFFS2_FIRST_BANK].size = 1024*1024*2; /* only read kernel single meg partition */
- flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024; /* 1024 blocks in 16meg chip (use less for raw/copied partition) */
- flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */
-#endif
-}
-#endif